IS66WVE2M16EALL Datasheet, PDF (21/31 Pages) Integrated Silicon Solution, Inc – Asynchronous and page mode interface

IS66/67WVE2M16EALL/BLL/CLL
AC Characteristics
Table 12. Asynchronous READ Cycle Timing Requirements
Symbol
Parameter
-55
Min
Max
t_AA
Address Acess Time
55
t_APA
Page access Time
20
t_BA
LB# /UB# access Time
55
t_BHZ
LB#/UB# disable to High-Z
output
8
t_BLZ
LB#/UB# enable to Low-Z
output
10
t_CEM
Maximum CE# pulse width
8
t_CO
Chip select access time
55
t_HZ
Chip disable to High-Z output
8
t_LZ
Chip enable to Low-Z output
10
t_OE
Output enable to valid output
20
t_OH
Output hold from address
change
5
t_OHZ
Output disable to High-Z
output
8
t_OLZ
Output enable to Low-Z
output
3
t_PC
Page cycle time
20
t_RC
Read cycle time
55
t_CPH
CE# HIGH time Read
5
-70
Min
Max
70
20
70
8
10
8
70
8
10
20
5
8
3
20
70
5
Unit Notes
ns
ns
ns
ns
1
ns
2
us
ns
ns
1
ns
2
ns
ns
ns
1
ns
2
ns
ns
3
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
3. Address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with CE#
HIGH transition.
Rev. 0D | November 2014
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