IS66WVE2M16EALL Datasheet, PDF (20/31 Pages) Integrated Silicon Solution, Inc – Asynchronous and page mode interface

IS66/67WVE2M16EALL/BLL/CLL
Table 10. Deep Power-Down Specifications
Description
Deep Power-Down
(ALL/CLL)
Deep Power-Down
(BLL)
Conditions
VIN=VDDQ or 0V; +25°C
ZZ# = 0V, CR[4] = 0
VIN=VDDQ or 0V; +25°C
ZZ# = 0V, CR[4] = 0
Symbol
Izz
Izz
TYP
3
10
MAX
10
20
Unit
uA
uA
Table 11. Capacitance
Description
Input Capacitance
Input/Output Capacitance (DQ)
Conditions
TC=+25°C;
f=1Mhz;
VIN=0V
Symbol
C_IN
C_IO
MIN
2.0
3.5
MAX
6.5
6.5
Unit
pF
pF
Note
1
1
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
Figure 8. AC Input/Output Reference Waveform
VDDQ
∫∫
VDDQ/2² Input¹
VSS
Test Points
∫∫
VDDQ/2³ Output
Notes:
1. AC test inputs are driven at VDDQ for a logic 1 and VSS for a logic 0. Input rise and fall times
(10% to 90%) < 1.6ns.
2. Input timing begins at VDDQ/2.
3. Output timing ends at VDDQ/2.
Figure 9. Output Load Circuit
DUT
Test Point
50Ω
30pF
VDDQ/2
Rev. 0D | November 2014
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