IS66WVE2M16EALL Datasheet, PDF (15/31 Pages) Integrated Silicon Solution, Inc – Asynchronous and page mode interface

IS66/67WVE2M16EALL/BLL/CLL
Table 3. Configuration Register
Bit Number
20 – 8
7
6–5
Definition
Reserved
Page
TCR
4
Sleep
3
Reserved
Remark
All Must be set to “0”
0 = Page mode disabled (default)
1 = Page mode enabled
1 1 = +85°C (default)
0 0 = +70°C
0 1 = +45°C
1 0 = +15°C
0 = DPD enabled
1 = PAR enabled (default)
Must be set to “0”
2–0
PAR¹
000 = Full array (default)
100 = None of array
Notes :
1. Use of other setting will result in full-array refresh coverage.
Rev. 0D | November 2014
www.issi.com - [e-mail]
15