IS62WV51216ALL Datasheet, PDF (10/16 Pages) Integrated Silicon Solution, Inc – 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62WV51216ALL, IS62WV51216BLL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
tWC
Write Cycle Time
tSCS1/tSCS2 CS1/CS2 to Write End
tAW
Address Setup Time to Write End
tHA
Address Hold from Write End
tSA
Address Setup Time
tPWB
LB, UB Valid to End of Write
tPWE⁽⁴⁾
WE Pulse Width
tSD
Data Setup to Write End
tHD
Data Hold from Write End
tHZWE⁽³⁾ WE LOW to High-Z Output
tLZWE⁽³⁾ WE HIGH to Low-Z Output
45ns
Min. Max.
45 —
35 —
35 —
0—
0—
35 —
35 —
20 —
0—
— 20
5—
55 ns
Min. Max.
55 —
45 —
45 —
0—
0—
45 —
40 —
25 —
0—
— 20
5—
70 ns
Min. Max.
Unit
70 —
ns
60 —
ns
60 —
ns
0—
ns
0—
ns
60 —
ns
50 —
ns
30 —
ns
0—
ns
— 30
ns
5—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. tPWE > tHZWE + tSD when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1^(1,2) (CS1 Controlled, OE = HIGH or LOW)
ADDRESS
CS1
CS2
WE
LB, UB
DOUT
DIN
tWC
tSCS1
tHA
tSCS2
tAW
tPWE
tPWB
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at
least one of the LB and UB inputs being in the LOW state.
2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
02/24/05