IS62WV20488ALL Datasheet, PDF(10/16 Page) Integrated Silicon Solution, Inc – 2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM

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IS62WV20488ALL Datasheet, PDF (10/16 Pages) Integrated Silicon Solution, Inc – 2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM

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IS62WV20488ALL

IS62WV20488BLL

ISSI Â®

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol Parameter

25 ns

35 ns

Min. Max.

Unit

tWC

Write Cycle Time

tSCS1/tSCS2 CS1/CS2 to Write End

tAW

Address Setup Time to Write End

15 â

tHA

Address Hold from Write End

tSA

Address Setup Time

tPWE(4)

WE Pulse Width

tSD

Data Setup to Write End

tHD

Data Hold from Write End

tHZWE(3) WE LOW to High-Z Output

â 12

â 20

tLZWE(3) WE HIGH to Low-Z Output

Notes:

1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof 0.4toVDD-0.2V/0.4VtoVDD-0.3Vand

output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the

write.

3. TestedwiththeloadinFigure2.TransitionismeasuredÂ±500mVfromsteady-statevoltage.Not100%tested.

4. tPWE > tHZWE + tSD when OE is LOW.

AC WAVEFORMS

WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)

ADDRESS

CS1

CS2

DOUT

DIN

tWC

tSCS1

tHA

tSCS2

tAW

tPWE

tSA

tHZWE

DATA UNDEFINED

HIGH-Z

tLZWE

tSD

tHD

DATA-IN VALID

Integrated Silicon Solution, Inc. â www.issi.com â 1-800-379-4774

Rev. 00B

06/21/06

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