X9261 Datasheet, PDF (9/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus

Figure 2. Two-Byte Instruction Sequence
X9261
CS
SCK
SI
0 1 0 10
ID3 ID2 ID1 ID0 0
Device ID
0
0
0 ^{A1 A0} I3 I2 I1 I0 RB RA
P0
Internal
Address
Instruction
Opcode
Register Pot/WCR
Address Address
Figure 3. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 _{0 0 A1 A0}
I3 I2
0
I1 I0 ^{RB RA P0}
D7 D6 D5 D4 D3 D2 D1 D0
Device ID
Internal
Address
Instruction
Opcode
Register Pot/WCR
Address Address
WCR[7:0]
or
Data Register Bit [7:0]
Figure 4. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 _{0 0} A1 A0
0
I3 I2 I1 I0 RB RA P0
XXXX XXXX
Don’t Care
Device ID
Internal
Address
Instruction Register Pot/WCR
Opcode
Address Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register Bit [7:0]
9
FN8171.2
September 14, 2005