X9261 Datasheet, PDF (10/21 Pages) Intersil Corporation – Single Supply/Low Power/256-Tap/SPI Bus

X9261
Figure 5. Three-Byte Instruction Sequence (Read Status Register)
CS
SCL
SI
0 1 0 1 00
1011
0
ID3 ID2 ID1 ID0 0 0 A1 A0 I3 I2 I1 I0 RB RA _P0
0000
000
WIP
Device ID
Internal
Address
Instruction
Opcode
Register Pot/WCR
Address Address
Status
Bit
Figure 6. Increment/Decrement Instruction Sequence
CS
SCL
SI
0 1 0 1 00
0
ID3 ID2 ID1 ID0 0 0 _{A1 A0}
I2 I3 I1 I0 RB RA P0
II
ID
D
Device ID
Internal
Address
Instruction
Register Pot/WCR
NN
CC
NE
CC
E
C
Opcode
Address Address 1 2
n1
n
Figure 7. Increment/Decrement Timing Limits
SCK
SI
RW
VOLTAGE OUT
INC/DEC CMD ISSUED
tWRID
10
FN8171.2
September 14, 2005