X80130 Datasheet, PDF (9/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors

X80130, X80131, X80132, X80133, X80134
Description
The X80130 is a voltage supervisor/sequencer with three
built in voltage monitors. This allows the designer to monitor
up to three voltages and sequence up to four events.
Low voltage detection circuitry protects the system from
power supply failure or “brown out” conditions, resetting the
system and resequencing the voltages when any of the
monitored inputs fall below the minimum threshold level. The
RESET pin is active until all monitored voltages reach proper
operating levels and stabilize for a selectable period of time.
Five common low voltage combinations are available,
however, Intersil’s unique circuits allow the any voltage
monitor threshold to be reprogrammed for special needs or
for applications requiring higher precision.
A manual reset input provides debounce circuitry for
minimum reset component count. Activating the manual
reset both controls the RESET output and resequences the
supplies through control of the ViGDO pins.
The X80130 has 2kb of EEPROM for system configuration,
manufacturing or maintenance information. This memory is
protected to prevent inadvertent changes to the contents.
Functional Description
Power On Reset and System Reset With Delay
Application of power to the X80130 activates a Power On
Reset circuit that pulls the RESET pin active. This signal, if
used, prevents the system microprocessor from starting to
operate while there is insufficient voltage on any of the
supplies. This circuit also does the following:
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
• It prevents communication to the EEPROM during
unstable power conditions, greatly reducing the likelihood
of data corruption on power up.
• It allows time for all supplies to turn on and stabilize prior
to system initialization.
The POR/RESET circuit is activated when all voltages are
within specified ranges and the V1GDO, V3GDO, and
V4GDO time-out conditions are met. The POR/RESET
circuit will then wait t_SPOR and de-assert the RESET pin.
The POR delay may be changed by setting the TPOR bits in
register CR2. The delay can be set to 100ms, 500ms, 1
second, or 5 seconds.
TPOR1
0
0
1
1
TABLE 1. POR RESET DELAY OPTIONS
TPOR0
t_SPOR DELAY BEFORE RESET
ASSERTION
0
100 miliseconds (default)
1
500 miliseconds
0
1 second
1
5 seconds
Manual Reset
The manual reset option allows a hardware reset of the
power sequencing pins. These can be used to recover the
system in the event of an abnormal operating condition.
Activating the MR pin for more than 5µs sets all of the
ViGDO outputs and the RESET output active (LOW). When
MR is released (and if all supplies are still at their proper
operating voltage) then the ViGDO and RESET pins will be
released after their programmed delay periods.
Triple Voltage Monitoring
X80130 monitors 3 voltage inputs. When the ViMON (i =1, 3,
4) input is detected to be above the input threshold, the
output ViGDO (i =1, 3, 4) goes inactive (LOW). The ViGDO
signal is de-asserted after a delay of 100ms. This delay can
be changed on each ViGDO output individually with bits in
register CR3. The delay can be 100ms, 500ms, 1s and 5s.
Each ViGDO signal remains active until its associated
ViMON input rises above the threshold.
TABLE 2. ViGDO OUTPUT TIME DELAY OPTIONS
TiD1
0
TiD0
0
t_DELAYi
100ms (default)
0
1
500ms
1
0
1 secs
1
1
5 secs
where i is the specific voltage monitor (i = 1, 3, 4).
Fault Detection
The X80130 contains a Fault Detection Register (FDR) that
provides the user the status of the causes for a RESET pin
active (See Table 20).
At power-up, the FDR is defaulted to all “0”. The system
needs to initialize the register to 0Dh before the actual
monitoring can take place. In the event that any one of the
monitored sources fail, the corresponding bit in the register
changes from a “1” to a “0” to indicate the failure. When a
RESET is detected by the main controller, the controller
should read the FDR and note the cause of the fault. After
reading the register, the controller can reset the register bit
back to all “1” in preparation for future failure conditions.
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FN8152.0
January 20, 2005