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| X80130 Datasheet, PDF (7/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors | |||
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Timing Diagrams
X80130, X80131, X80132, X80133, X80134
tBUF
SCL
tSU:STA
SDA IN
tF
tSU:DAT
tHD:STA
SDA OUT
tHIGH
tLOW
tR
tHD:DAT
tSU:STO
tAA tDH
FIGURE 4. BUS TIMING
tBUF
tHD:STO
tHD:DAT
SCL
SDA IN
WP
A1, A0
VP
START
tSU:WP
tSU:ADR
tSU:VP
Clk 1
Slave Address Byte
Clk 9
tHD:WP
tHD:ADR
FIGURE 5. WP, A0, A1, VP PIN TIMING
STOP
tWC
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Condition
Start
Condition
FIGURE 6. WRITE CYCLE TIMING
7
FN8152.0
January 20, 2005
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