X80130 Datasheet, PDF (8/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors

X80130, X80131, X80132, X80133, X80134
Symbol Table
WAVEFORM INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Pinout
QFN package
(Top view)
V4GDO
V4MON
V3GDO
V3MON
DNC
20 19 18 17 16
1
15
2
14
3 ^{(5mm x 5mm)} ₁₃
4
12
5
11
6 7 8 9 10
WP
RESET
V1GDO
V1MON
SCL
Pin Descriptions
PIN
NAME
1
V4GDO
2
V4MON
3
V3GDO
4
V3MON
5
DNC
6
V_P
7
V_CC
8
DNC
9
A1
10
SDA
11
SCL
12
V1MON
13
V1GDO
14
RESET
15
WP
16
MR
17
V_SS
18
NC
19
A0
20
V_CC
DESCRIPTION
V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than V_REF4
and goes LOW when V4MON is greater than V_REF4. There is user selectable delay circuitry on this pin.
V4 Voltage Monitor Input. Third voltage monitor pin. If unused connect to V_CC.
V3 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V3MON is less than V_REF3
and goes LOW when V3MON is greater than V_REF3. There is user selectable delay circuitry on this pin.
V3 Voltage Monitor Input. Second voltage monitor pin. If unused connect to V_CC.
Do Not Connect.
EEPROM programming Voltage.
Connect to V_CC.
Do Not Connect.
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80130 devices to be used on the same SMBus serial interface.
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device.
It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to V_CC.
V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than V_REF1
and goes LOW when V1MON is greater than V_REF1. There is user selectable delay circuitry on this pin.
RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive
and the power sequencing is complete. This pin will be released after a programmable delay.
Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the
device. It has an internal pull-down resistor. (>10MΩ typical)
Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5µsecs. It has an
internal pull-down resistor. (>10MΩ typical)
Ground Input.
No Connect. No internal connections.
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80130 devices to be used on the same SMBus serial interface.
Supply Voltage.
8
FN8152.0
January 20, 2005