X80130 Datasheet, PDF (13/18 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Triple Programmable Time Delay with Local/Remote Voltage Monitors

X80130, X80131, X80132, X80133, X80134
BYTE
ADDR. NAME
00H CR0
01H CR1
02H CR2
03H CR3
FF
FDR
CONTROI/STATUS
Write Enable
EEPROM Block
Control
POR Timing
ViGDO TIme Delay
Fault Detection
Register
TABLE 4. REGISTER ADDRESS MAP
BIT
7
6
5
4
3
2
WEL
0
0
0
0
0
WPEN
0
0
BP1
BP0
0
0
T4D1
0
0
T4D0
0
0
T3D1
0
0
T3D0
0
TPOR1
0
V40S
TPOR0
0
V30S
1
0
0
0
T1D1
0
0
0
0
0
T1D0
V10S
MEMORY
TYPE
Volatile
EEPROM
EEPROM
EEPROM
Volatile
TABLE 5. HARDWARE/SOFTWARE CONTROL AND FAULT DETECTION BITS SUMMARY
OPERATION
CONTROL
LOCATION(S)
/STATUS _{REGISTER BITS}
SOFTWARE CONTROL BITS
DESCRIPTION (SEE FUNCTIONAL FOR DETAILS)
EEPROM Write Enable
WEL
CR0
7
WEL = 1 enables write operations to the control registers and EEPROM.
WEL = 0 prevents write operations.
EEPROM Write Protect WPEN
CR1
7
WPEN = 1 (and WP pin HIGH) prevents writes to the control registers and the
EEPROM.
EEPROM Block Protect
BP1
BP0
CR1
4:3
BP1=0, BP0=0 : No EEPROM memory protected.
BP1=0, BP0=1 : Upper 1/4 of EEPROM memory protected
BP1=1, BP0=0 : Upper 1/2 of EEPROM memory protected.
BP1=1, BP0=1 : All of EEPROM memory protected.
RESET Time Delay
TPOR0
TPOR1
CR2
3:2
TPOR1=0, TPOR0=0 : RESET delay = 100ms
TPOR1=0, TPOR0=1 : RESET delay = 500ms
TPOR1=1, TPOR0=0 : RESET delay = 1s
TPOR1=1, TPOR0=1 : RESET delay = 5s
V1GDO Time Delay
V3GDO Time Delay
T1D0
T1D1
T3D0
T3D1
CR3
CR3
1:0
TiD1=0, TiD0=0 : ViGDO delay = 100ms
TiD1=0, TiD0=1 : ViGDO delay = 500ms
TiD1=1, TiD0=0 : ViGDO delay = 1s
5:4
TiD1=1, TiD0=1 : ViGDO delay = 5s
V4GDO Time Delay
T4D0
CR3
7:6
T4D1
STATUS BITS
1st Voltage Monitor
V1OS
FDR
0
V1OS = 0 : V1GDO pin has been asserted (must be preset to 1).
3rd Voltage Monitor
V3OS
FDR
2
V3OS = 0 : V3GDO pin has been asserted (must be preset to 1).
4th Voltage Monitor
V4OS
FDR
3
V4OS = 0 : V4GDO pin has been asserted (must be preset to 1).
Bus Interface Information
Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a STOP condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a STOP condition.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (See Figure 11).
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH. The
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FN8152.0
January 20, 2005