ISL78840ASEH Datasheet, PDF (9/15 Pages) Intersil Corporation – Radiation Hardened, High Performance Industry Standard Single-Ended Current Mode PWM Controller

ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
To optimize noise immunity, bypass V_DD to GND with a ceramic
capacitor as close to the V_DD and GND pins as possible.
V_REF - The 5.00V reference voltage output. +1.0/-1.5% tolerance
over line, load and operating temperature. The recommended
bypass to GND cap is in the range 0.1µF to 0.22µF. A typical
value of 0.15µF can be used.
Functional Description
Features
The ISL7884xASEH current mode PWM makes an ideal choice
for low-cost flyback and forward topology applications. With its
greatly improved performance over industry standard parts, it is
the obvious choice for new designs or existing designs which
require updating.
Oscillator
The ISL7884xASEH has a sawtooth oscillator with a
programmable frequency range to 2MHz, which can be
programmed with a resistor from V_REF and a capacitor to GND on
the RTCT pin. (Please refer to Figure 4 for the resistor and
capacitance required for a given frequency).
Soft-Start Operation
Soft-start must be implemented externally. One method,
illustrated below, clamps the voltage on COMP.
V_REF
D₁
R₁
COMP
Q₁
GND
C₁
FIGURE 5. SOFT-START
The COMP pin is clamped to the voltage on capacitor C₁ plus a
base-emitter junction by transistor Q₁. C₁ is charged from V_REF
through resistor R₁ and the base current of Q₁. At power-up C₁ is
fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As
C₁ charges, the voltage on COMP increases, and the duty cycle
increases in proportion to the voltage on C₁. When COMP
reaches the steady state operating point, the control loop takes
over and soft-start is complete. C₁ continues to charge up to
V_REF and no longer affects COMP. During power-down, diode D₁
quickly discharges C₁ so that the soft-start circuit is properly
initialized prior to the next power-on sequence.
Gate Drive
The ISL7884xASEH is capable of sourcing and sinking 1A peak
current. To limit the peak current through the IC, an optional
external resistor may be placed between the totem-pole output of
the IC (OUT pin) and the gate of the MOSFET. This small series
resistor also damps any oscillations caused by the resonant tank
of the parasitic inductances in the traces of the board and the
FET’s input capacitance. TID environment of >50krads requires
the use of a bleeder resistor of 10k from the OUT pin to GND.
Slope Compensation
For applications where the maximum duty cycle is less than 50%,
slope compensation may be used to improve noise immunity,
particularly at lighter loads. The amount of slope compensation
required for noise immunity is determined empirically, but is
generally about 10% of the full scale current feedback signal. For
applications where the duty cycle is greater than 50%, slope
compensation is required to prevent instability.
Slope compensation may be accomplished by summing an
external ramp with the current feedback signal or by subtracting
the external ramp from the voltage feedback error signal. Adding
the external ramp to the current feedback signal is the more
popular method.
From the small signal current-mode model [1] it can be shown
that the naturally-sampled modulator gain, Fm, without slope
compensation is calculated in Equation 6:
Fm
=
--------¹---------
Sntsw
(EQ. 6)
where Sn is the slope of the sawtooth signal and tsw is the
duration of the half-cycle. When an external ramp is added, the
modulator gain becomes Equation 7:
Fm
=
-----------------¹-------------------
(Sn + Se)tsw
=
------------¹-------------
m_cSntsw
(EQ. 7)
where Se is slope of the external ramp and becomes Equation 8:
m_c
=
1
+
S_-----e_--
Sn
(EQ. 8)
The criteria for determining the correct amount of external ramp
can be determined by appropriately setting the damping factor of
the double-pole located at the switching frequency. The
double-pole will be critically damped if the Q-factor is set to 1,
over-damped for Q < 1, and under-damped for Q > 1. An
under-damped condition may result in current loop instability.
Q = -_π---₍---_m-----_c---₍--₁-----–--¹---_D-----₎---–-----₀---_.--₅----₎
(EQ. 9)
where D is the percent of on-time during a switching cycle.
Setting Q = 1 and solving for Se yields Equation 10:
e
=
S_n
⎛
⎝
⎛
⎝
1_--
π
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
(EQ. 10)
Since Sn and Se are the on-time slopes of the current ramp and
the external ramp, respectively, they can be multiplied by t_ON to
obtain the voltage change that occurs during t_ON.
V_e
=
V_n
⎛
⎝
⎛
⎝
1_-π-
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
(EQ. 11)
where V_n is the change in the current feedback signal (ΔI) during
the on-time and Ve is the voltage that must be added by the
external ramp.
9
FN7952.0
May 29, 2012