ISL78840ASEH Datasheet, PDF (10/15 Pages) Intersil Corporation – Radiation Hardened, High Performance Industry Standard Single-Ended Current Mode PWM Controller

ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
For a flyback converter, Vn can be solved in terms of input
voltage, current transducer components, and primary
inductance, yielding Equation 12:
V_e
=
D_------⋅_---T_{----S----W-------}⋅_---V_{----I--N-----}⋅_---R_{-----C----S--}
L_p
⎛
⎝
⎛
⎝
1_--
π
+
0.5_⎠⎞
------¹-------
1–D
–
1_⎠⎞
V
(EQ. 12)
where R_CS is the current sense resistor, T_sw is the switching
period, L_p is the primary inductance, V_IN is the minimum input
voltage, and D is the maximum duty cycle.
The current sense signal at the end of the ON time for CCM
operation is Equation 13:
V_CS
=
N_-----S-----⋅_---R_{-----C----S--}
N_P
⎛
⎝⎜^IO
+
-⁽--¹-----–----^D-----⁾--₂--^â‹--_L-^V--_s--^O-----^â‹---^T----^s---^w-- _{⎠⎟⎞}
V
(EQ. 13)
where V_CS is the voltage across the current sense resistor, L_s is
the secondary winding inductance, and I_O is the output current at
current limit. Equation 13 assumes the voltage drop across the
output rectifier is negligible.
Since the peak current limit threshold is 1.00V, the total current
feedback signal plus the external ramp voltage must sum to this
value when the output load is at the current limit threshold as:
V_e + V_CS = 1V
(EQ. 14)
shown in Equation 14.
Substituting Equations 12 and 13 into Equation 14 and solving
for R_CS yields Equation 15:
R_CS
=
---------------------------------------------------------------------------¹-----------------------------------------------------------------------------
D_------⋅_---T_{----s---w------}⋅_---V_----I--N--
L_p
⋅
⎛
⎜
⎜
⎝
-^{1π-------+----0}----^.-⁵--
1–D
⎞
–1_⎟⎟
⎠
+
-^N----^s-
N_p
⋅
⎛
⎝⎜^IO
+
(_---1_{-----–----}D_-----)_--2--⋅_--L-V_--s--O-----⋅_---T_{----s---w-- ⎠⎟⎞}
(EQ. 15)
Adding slope compensation is accomplished in the
ISL7884xASEH using an external buffer transistor and the RTCT
signal. A typical application sums the buffered RTCT signal with
the current sense feedback and applies the result to the CS pin
as shown in Figure 6.
V_REF
R9
CS
R6
RTCT
C4
FIGURE 6. SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter (R₆
and C₄) placed on the CS pin, the value of R₉ required to add the
appropriate external ramp can be found by superposition.
V_e
=
2_----._--0_---5_----D_------⋅_--R_-----6-
R₆ + R₉
V
(EQ. 16)
The factor of 2.05 in Equation 16 arises from the peak amplitude
of the sawtooth waveform on RTCT minus a base-emitter junction
drop. That voltage multiplied by the maximum duty cycle is the
voltage source for the slope compensation. Rearranging to solve
for R₉ yields Equation 17:
R₉
=
-⁽--²---^.--⁰---⁵----^D------–----^V-----^e---⁾----^â‹---^R----⁶-
V_e
Ω
(EQ. 17)
The value of R_CS determined in Equation 15 must be rescaled so
that the current sense signal presented at the CS pin is that
predicted by Equation 13. The divider created by R₆ and R₉
makes this necessary.
R′_CS
=
R_{-----6-----+----}R_-----9-
R₉
⋅
R_CS
(EQ. 18)
Example:
V_IN = 12V
V_O = 48V
L_s = 800µH
Ns/Np = 10
Lp = 8.0µH
I_O = 200mA
Switching Frequency, f_sw = 200kHz
Duty Cycle, D = 28.6%
R₆ = 499Ω
Solve for the current sense resistor, R_CS, using Equation 15.
R_CS = 295mΩ
Determine the amount of voltage, Ve, that must be added to the
current feedback signal using Equation 12.
Ve = 92.4mV
Using Equation 17, solve for the summing resistor, R₉, from CT to
CS.
R₉ = 2.67kΩ
Determine the new value of R_CS (R’_CS) using Equation 18.
R’_CS = 350mΩ
Additional slope compensation may be considered for design
margin. The above discussion determines the minimum external
ramp that is required. The buffer transistor used to create the
external ramp from RTCT should have a sufficiently high gain
(>200) so as to minimize the required base current. Whatever
base current is required reduces the charging current into RTCT
and will reduce the oscillator frequency.
10
FN7952.0
May 29, 2012