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ISL78840ASEH Datasheet, PDF (7/15 Pages) Intersil Corporation – Radiation Hardened, High Performance Industry Standard Single-Ended Current Mode PWM Controller
ISL78840ASEH, ISL78841ASEH, ISL78843ASEH, ISL78845ASEH
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. VDD = 13.2V, RT = 10kΩ, CT = 3.3nF, TA = -55 to +125°C. Typical values are at TA = +25°C. Boldface limits apply over
the operating temperature range, -55 to +125°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 10)
TYP
(Note 10)
UNITS
Gain, ACS = ΔVCOMP/ΔVCS
CS to OUT Delay
0 < VCS < 910mV, VFB = 0V
2.75
2.82
3.15
V/V
-
35
55
ns
ERROR AMPLIFIER
Open Loop Voltage Gain
(Note 8)
-
90
-
dB
Unity Gain Bandwidth
(Note 8)
-
1.5
-
MHz
Reference Voltage, VREF
FB Input Bias Current, FBIIB
COMP Sink Current
COMP Source Current
COMP VOH
COMP VOL
PSRR
VFB = VCOMP
2.475
2.500
2.530
V
VFB = 0V
-1.0
-0.2
1.0
µA
VCOMP = 1.5V, VFB = 2.7V
1.0
-
-
mA
VCOMP = 1.5V, VFB = 2.3V
-0.4
-
-
mA
VFB = 2.3V
4.80
-
VREF
V
VFB = 2.7V
0.4
-
1.0
V
Frequency = 120Hz, VDD = 9V to 13.2V
-
80
-
dB
(Note 8)
OSCILLATOR
Frequency Accuracy
Frequency Variation with VDD
Temperature Stability
Initial, TA = +25°C
TA= +25°C, (f13.2V - f9V)/f12V
(Note 8)
48
51
53
kHz
-
0.2
1.0
%
-
5
-
%
Amplitude, Peak-to-Peak
Static Test
-
1.75
-
V
RTCT Discharge Voltage (Valley Voltage)
Static Test
-
1.0
-
V
Discharge Current
RTCT = 2.0V
6.5
7.8
8.5
mA
OUTPUT
Gate VOH
Gate VOL
Peak Output Current
Rise Time
Fall Time
OUTPUT OFF state leakage
PWM
VDD to OUT, IOUT = -100mA
OUT to GND, IOUT = 100mA
COUT = 1nF (Note 8)
COUT = 1nF
COUT = 1nF
VDD = 5V
-
1.0
2.0
V
-
1.0
2.0
V
-
1.0
-
A
-
35
60
ns
-
20
40
ns
-
-
50
µA
Maximum Duty Cycle
(ISL78840A, ISL78843A)
COMP = VREF
94.0
96.0
-
%
Maximum Duty Cycle
(ISL78841A, ISL78845A)
COMP = VREF
47.0
48.0
-
%
Minimum Duty Cycle
COMP = GND
-
-
0
%
NOTES:
7. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
8. Limits established by characterization and are not production tested.
9. SEE tests performed with VREF bypass capacitor of 0.22µF and FSW = 200kHz. SEB/L tests done on a standalone open loop configuration. SET tests
done in a closed loop configuration. For SEL no hard latch requiring manual intervention were observed. For more information see:
ISL7884xASRH SEE Test Report.
10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7
FN7952.0
May 29, 2012