ISL70001SRH Datasheet, PDF (9/16 Pages) Intersil Corporation – Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs

ISL70001SRH
Functional Description
The ISL70001SRH is a monolithic, fixed frequency,
current-mode synchronous buck regulator with user
configurable power blocks. Two ISL70001SRH devices
can be used to provide a total DC/DC solution for
FPGAs, CPLDs, DSPs and CPUs.
pilot. If V_OUT is low, the current level of the pilot is
increased and the trip off current level of the output is
increased. The increased output current raises V_OUT
until it is in agreement with the reference voltage.
Output Voltage Selection
PVIN1
LX1
PGND1
POWER BLOCK 1 POWER BLOCK 6
PVIN6
LX6
PGND6
PVIN2
LX2
PGND2
POWER BLOCK 2 POWER BLOCK 5
PVIN5
LX5
PGND5
PVIN3
LX3
PGND3
POWER BLOCK 3 POWER BLOCK 4
PVIN4
LX4
PGND4
FIGURE 3. POWER BLOCK DIAGRAM
Power Blocks
The power output stage of the regulator consists of six
1A capable power blocks that are paralleled to provide
full 6A output current capability. The block diagram in
Figure 3 shows a top level view of the individual power
blocks.
Each power block has a power supply input pin, PVINx,
a phase output pin, LXx, and a power supply ground
pin, PGNDx. All PVINx pins must be connected to a
common power supply rail and all PGNDx pins must be
connected to a common ground. LXx pins should be
connected to the output inductor based on the required
load current, but must include the LX4 pin. For
example, if 3A of output current is needed, any three
LXx pins can be connected to the inductor as long as
one of them is the LX4 pin. The unused LXx pins
should be left unconnected. Connecting all six LXx pins
to the output inductor provides a maximum 6A of
output current. See the “Typical Application Schematic”
on page 5 for pin connection guidance.
A scaled pilot device associated with each power block
provides current feedback. Power block 4 contains the
master pilot device and this is why it must be
connected to the output inductor.
Main Control Loop
During normal operation, the internal top power switch
is turned on at the beginning of each clock cycle.
Current in the output inductor ramps up until the
current comparator trips and turns off the top power
MOSFET. The bottom power MOSFET turns on and the
inductor current ramps down for the rest of the cycle.
The current comparator compares the output current
at the ripple current peak to a current pilot. The error
amplifier monitors V_OUT and compares it with an
internal reference voltage. The output voltage of the
error amplifier drives a proportional current to the
V_REF = 0.6V
C_REF = 220nF
R_T = 1k
C_C = 4.7nF
ERROR
AMPLIFIER
-
+ ^VREF
LXx ^LOUT
V_OUT
C_OUT
R_T C_C
FB
REF
R_B
C_REF
FIGURE 4. OUTPUT VOLTAGE SELECTION
The output voltage of the ISL70001SRH can be
adjusted using an external resistor divider as shown in
Figure 4. R_T should be selected as 1kΩ to mitigate SEE.
R_T should be shunted by a 4.7nF ceramic capacitor, C_C,
to mitigate SEE and to improve loop stability margins.
The REF pin should be bypassed to AGND with a 220nF
ceramic capacitor to mitigate SEE. It should be noted
that no current (sourcing or sinking) is available from
the REF pin. R_B can be determined from Equation 3.
The designer can configure the output voltage from
0.8V to 85% of the input voltage.
R_B
=
R_T
⋅
------------^V----^R----^E----^F-------------
V_OUT – V_REF
(EQ. 3)
Switching Frequency/Synchronization
The ISL70001SRH features an internal oscillator
running at a fixed frequency of 1MHz ±15% over
recommended operating conditions. The regulator can
be configured to run from the internal oscillator or can
be synchronized to another ISL70001SRH or an SEE
hardened external clock with a frequency range of
1MHz ±20%.
To run the regulator from the internal oscillator,
connect the M/S pin to DVDD. In this case the output
of the internal oscillator appears on the SYNC pin. To
synchronize the regulator to the SYNC output of
another ISL70001SRH regulator or to an SEE hardened
external clock, connect the M/S pin to DGND. In this
case the SYNC pin is an input that accepts an external
synchronizing signal. When synchronizing multiple
devices, Slave regulators are synchronized 180°
out-of-phase with respect to the SYNC output of a
Master regulator or to an external clock.
Operation Initialization
The ISL70001SRH initializes based on the state of the
power-on reset (POR) monitor of the PVINx inputs and
the state of the EN input. Successful initialization
prompts a soft-start interval and the regulator begins
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FN6947.0
December 15, 2009