ISL70001SRH Datasheet, PDF (12/16 Pages) Intersil Corporation – Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs

ISL70001SRH
Component Selection Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a power
converter. It is assumed the reader is familiar with
many of the basic skills and techniques referenced
below. In addition to this guide, Intersil provides a
complete evaluation board that includes schematic,
BOM, and an example PCB layout.
Output Filter Design
The output inductor and the output capacitor bank
together form a low-pass filter responsible for
smoothing the pulsating voltage at the phase node.
The filter must also provide the transient energy until
the regulator can respond. Since the filter has low
bandwidth relative to the switching frequency, it limits
the system transient response. The output capacitors
must supply or sink current while the current in the
output inductor increases or decreases to meet the
load demand.
OUTPUT CAPACITOR SELECTION
The critical load parameters in choosing the output
capacitors are the maximum size of the load step
(ΔI_STEP), the load-current slew rate (di/dt), and the
maximum allowable output voltage deviation under
transient loading (ΔV_MAX). Capacitors are characterized
according to their capacitance, ESR (Equivalent Series
Resistance) and ESL (Equivalent Series Inductance).
At the beginning of a load transient, the output
capacitors supply all of the transient current. The output
voltage will initially deviate by an amount approximated
by the voltage drop across the ESL. As the load current
increases, the voltage drop across the ESR increases
linearly until the load current reaches its final value.
Neglecting the contribution of inductor current and
regulator response, the output voltage initially deviates
by an amount shown in Equation 8.
ΔV_MAX ≈
ESL × -^d---ⁱ
dt
+ [ESR × ΔI_STEP]
(EQ. 8)
The filter capacitors selected must have sufficiently low
ESL and ESR such that the total output voltage
deviation is less than the maximum allowable ripple.
Most capacitor solutions rely on a mixture of high
frequency capacitors with relatively low capacitance in
combination with bulk capacitors having high
capacitance but larger ESR. Minimizing the ESL of the
high-frequency capacitors allows them to support the
output voltage as the current increases. Minimizing the
ESR of the bulk capacitors allows them to supply the
increased current with less output voltage deviation.
Ceramic capacitors with X7R dielectric are
recommended. Alternately, a combination of low ESR
solid tantalum capacitors and ceramic capacitors with
X7R dielectric may be used.
The ESR of the bulk capacitors is responsible for most
of the output voltage ripple. As the bulk capacitors sink
and source the inductor AC ripple current, a voltage,
V_P-P(MAX), develops across the bulk capacitor
according to Equation 9.
V_P-P(MAX) = ESR ×
(_---V_{----I--N-----–-----}V_{----O-----U----T---})_---V_{----O-----U----T-}
L_OUT × f_s × V_IN
(EQ. 9)
Another consideration in selecting the output
capacitors is loop stability. The total output
capacitance sets the dominant pole of the PWM.
Because the ISL70001SRH uses integrated
compensation techniques, it necessary to restrict the
output capacitance in order to optimize loop stability.
The recommended load capacitance can be estimated
using Equation 10.
C_OUT
=
75μF × NumberofLXxPinsConnected × --¹---^.--⁸----^V----
V_OUT
(EQ.
10)
OUTPUT INDUCTOR SELECTION
Once the output capacitors are selected, the maximum
allowable ripple voltage, V_P-P(MAX), determines the
lower limit on the inductance as shown in Equation 11.
L_OUT ≥ ESR ×
-⁽---^V----^I--^N-----–-----^V----^O----^U----^T----⁾---^V----^O----^U----^T---
f_s × V_IN × V_P-P(MAX)
(EQ. 11)
Since the output capacitors are supplying a decreasing
portion of the load current while the regulator recovers
from the transient, the capacitor voltage becomes
slightly depleted. The output inductor must be capable
of assuming the entire load current before the output
voltage decreases more than ΔV_MAX. This places an
upper limit on inductance.
Equation 12 gives the upper limit on output inductance
for the case when the trailing edge of the current
transient causes the greater output voltage deviation
than the leading edge. Equation 13 addresses the
leading edge. Normally, the trailing edge dictates the
inductance selection because duty cycles are usually
<50%. Nevertheless, both inequalities should be
evaluated, and inductance should be governed based
on the lower of the two results. In each equation, L_OUT
is the output inductance, C_OUT is the total output
capacitance and ΔI_L(P-P) is the peak to peak ripple
current in the output inductor.
L_OUT
≤
2-----⋅_{---C-----O----U-----T----}⋅_{---V-----O----U----T--}
(ΔI_STEP)²
ΔV_MAX – (ΔI_L(P-P) ⋅ ESR)
(EQ. 12)
L_OUT
≤
---2-----^â‹---C----^O-----^U----^T----
(ΔI_STEP)²
ΔV_MAX – (ΔI_L(P-P) ⋅ ESR)
⎝⎛ ^{V I}
N
–
V_O
U
⎞
T_⎠
(EQ. 13)
The other concern when selecting an output inductor is
to insure there is adequate slope compensation when
the regulator is operated above 50% duty cycle. Since
the internal slope compensation is fixed, output
12
FN6947.0
December 15, 2009