ISL70001SRH Datasheet, PDF (10/16 Pages) Intersil Corporation – Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs

ISL70001SRH
slowly ramping the output voltage. Once the
commanded output voltage is within the proper
window of operation, the power-good signal changes
state from low to high indicating proper regulator
operation.
Power-On Reset
The POR circuitry prevents the controller from
attempting to soft-start before sufficient bias is
present at the PVINx pins.
The POR threshold of the PVINx pins is controlled by
the PORSEL pin. For a nominal 5V supply voltage,
PORSEL should be connected to DVDD. For a nominal
3.3V supply voltage, PORSEL should be connected to
DGND. For nominal supply voltages between 5V and
3.3V, PORSEL should be connected to DGND. The POR
rising and falling thresholds are shown in the
“Electrical Specifications” table on page 8.
Hysteresis between the rising and falling thresholds
insures that small perturbations on PVINx seen during
turn-on/turn-off of the regulator do not cause
inadvertent turn-off/turn-on of the regulator. When the
PVINx pins are below the POR rising threshold, the
internal synchronous power MOSFET switches are
turned off and the LXx pins are held in a
high-impedance state.
Enable and Disable
After the POR input requirement is met, the
ISL70001SRH remains in shutdown until the voltage at
the enable input rises above the enable threshold. As
shown in Figure 5, the enable circuit features a
comparator type input. In addition to simple logic
on/off control, the enable circuit allows the level of an
external voltage to precisely gate the turn-on/turn-off
of the regulator. An internal I_EN current sink with a
typical value of 11µA is only active when the voltage
on the EN pin is below the enable threshold. The
current sink pulls the EN pin low. As V_IN2 rises, the
enable level is not set exclusively by the resistor
divider from V_IN2. With the current sink active, the
enable level is defined by Equation 4. R1 is the resistor
from the EN pin to V_IN2 and R2 is the resistor from the
EN pin to the AGND pin.
V_ENABLE = V_R ⋅
1
+
R_-----1_--
R2
+ I_EN ⋅ R1
(EQ. 4)
Once the voltage at the EN pin reaches the enable
threshold, the I_EN current sink turns off.
With the part enabled and the I_EN current sink off, the
disable level is set by the resistor divider. The disable
level is defined by Equation 5.
V_DISABLE = V_R ⋅
1
+
R_-----1_--
R2
(EQ. 5)
The difference between the enable and disable levels
provides adjustable hysteresis so that noise on V_IN2
does not interfere with the enabling or disabling of the
regulator.
The EN pin should be bypassed to the AGND pin with a
10nF ceramic capacitor to mitigate SEE.
V_R = 0.6V
I_EN = 11µA
C_EN = 10nF
V_IN1
PVINx
POR
LOGIC
ENABLE
COMPARATOR
+
V_R
-
V_IN2
R1
EN
C_{EN R2}
I_EN
FIGURE 5. ENABLE CIRCUIT
Soft-Start
Once the POR and enable circuits are satisfied, the
regulator initiates a soft-start. Figure 6 shows that the
soft-start circuit clamps the error amplifier reference
voltage to the voltage on an external soft-start
capacitor connected to the SS pin. The soft-start
capacitor is charged by an internal I_SS current source.
As the soft-start capacitor is charged, the output
voltage slowly ramps to the set point determined by
the reference voltage and the feedback network. Once
the voltage on the SS pin is equal to the internal
reference voltage, the soft-start interval is complete.
The controlled ramp of the output voltage reduces the
inrush current during start-up. The soft-start output
ramp interval is defined in Equation 6 and is adjustable
from approximately 2ms to 200ms. The value of the
soft-start capacitor, C_SS, should range from 8.2nF to
8.2µF, inclusive. The peak inrush current can be
computed from Equation 7. The soft-start interval
should be selected long enough to insure that the peak
inrush current plus the peak output load current does
not exceed the overcurrent trip level of the regulator.
t_SS
=
C_SS
⋅
V_{-----R----E----F-}
I_SS
(EQ. 6)
I_INRUSH
=
C_O
U
T
⋅
V_{-----O----U----T--}
t_SS
(EQ. 7)
The soft-start capacitor is immediately discharged by a
2.2Ω resistor whenever POR conditions are not met or
EN is pulled low. The soft-start discharge time is equal
to 256 clock cycles.
10
FN6947.0
December 15, 2009