ISL70001SRH Datasheet, PDF (3/16 Pages) Intersil Corporation – Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs

Pin Configuration
ISL70001SRH
ISL70001SRH
(48 LD CQFP)
TOP VIEW
M/S
ZAP
TDI
TDO
PGOOD
SS
DVDD
DVDD
DGND
DGND
AGND
AGND
6 5 4 3 2 1 48 47 46 45 4443
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19 20 21 2223 24 25 26 2728 29 30
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
Pin Descriptions
PIN NUMBER
1, 2, 27, 28, 29,
30, 37, 38, 39,
40, 47, 48
3, 26, 31, 36,
41, 46
4, 5, 24, 25, 32,
33, 34, 35, 42,
43, 44, 45
6
7
8
9
10
PIN NAME
PGNDx
LXx
PVINx
SYNC
M/S
ZAP
TDI
TDO
DESCRIPTION
These pins are the power grounds associated with the corresponding internal power blocks.
Connect these pins directly to the ground plane. These pins should also connect to the
negative terminals of the input and output capacitors. Locate the input and output capacitors
as close as possible to the IC.
These pins are the outputs of the corresponding internal power blocks and should be
connected to the output filter inductor. Internally, these pins are connected to the synchronous
MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky
diode be connected from these pins to PGNDx. The Schottky diode should be located as close
as possible to the IC.
These pins are the power supply inputs to the corresponding internal power blocks. These pins
must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V.
Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to
the IC.
This pin is the synchronization I/O for the IC. When configured as an output (Master Mode),
this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave
Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock.
Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If
synchronizing to an external clock, the clock must be SEE hardened and the frequency must
be within the range of 1MHz ±20%.
This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For
SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode),
connect this pin to DGND.
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to
DGND.
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
3
FN6947.0
December 15, 2009