ISL70001SRH Datasheet, PDF (4/16 Pages) Intersil Corporation – Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs

ISL70001SRH
Pin Descriptions (Continued)
PIN NUMBER
11
12
PIN NAME
PGOOD
SS
DESCRIPTION
This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND
when the output voltage is outside a ±11% typical regulation window. This pin can be pulled
up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ
pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to
mitigate SEE.
This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the
soft-start output ramp time in accordance with Equation 1:
13, 14
15, 16
17, 18
19
20
21
22
23
DVDD
DGND
AGND
AVDD
REF
FB
EN
PORSEL
t_SS = C_SS ⋅ V_REF ⁄ I_SS
(EQ. 1)
Where:
t_SS = Soft-start output ramp time
C_SS = Soft-start capacitor
V_REF = Reference voltage (0.6V typical)
I_SS = Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
These pins are the bias supply inputs to the internal digital control circuitry. Connect these
pins together at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic
capacitor. Locate both filter components as close as possible to the IC.
These pins are the digital ground associated with the internal digital control circuitry. Connect
these pins directly to the ground plane.
These pins are the analog ground associated with the internal analog control circuitry. Connect
these pins directly to the ground plane.
This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin
to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as
close as possible to the IC.
This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic
capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate
SEE. No current (sourcing or sinking) is available from this pin.
This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from
FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2:
V_OUT = V_REF ⋅ [1 + (R_T ⁄ R_B)]
(EQ. 2)
Where:
V_OUT = Output voltage
V_REF = Reference voltage (0.6V typical)
R_T = Top divider resistor (Must be 1kΩ)
R_B = Bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across
RT to mitigate SEE and to improve stability margins.
This pin is the enable input to the IC. This is a comparator type input with a rising threshold
of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this
pin to AGND with a 10nF ceramic capacitor to mitigate SEE.
This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For
a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to
DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND.
4
FN6947.0
December 15, 2009