ISL6564 Datasheet, PDF (9/27 Pages) Intersil Corporation – Multi-Phase PWM Controller with Linear 6-bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

ISL6564
Electrical Specifications Operating Conditions: VCC = 5V or ICC < 25mA (Note 3).
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
PIN-ADJUSTABLE OFFSET
Voltage at OFS pin
Offset resistor connected to ground
388 400 412 mV
VCC = 5.000V, offset resistor connected to VCC
2.91 3.0 3.09 V
Maximum OFS Source and Sink Current
-
-
50
µA
OSCILLATOR
Accuracy
Adjustment Range
R_T = 100kΩ
260 300 345 kHz
0.08 -
1.5 MHz
Sawtooth Amplitude
-
2
-
V
Max Duty Cycle
- 66.7 -
%
ERROR AMPLIFIER
Open-Loop Gain
Open-Loop Bandwidth
Maximum Output Voltage
R_L = 10kΩ to ground
C_L = 100pF, R_L = 10kΩ to ground
-
80
-
dB
-
18
- MHz
4.0 4.3
-
V
Output High Voltage @ 2mA
3.7
-
-
V
Output Low Voltage @ 2mA
-
- 1.35 V
REMOTE-SENSE AMPLIFIER
Bandwidth
-
20
- MHz
Output Voltage @ 1mA load
VSEN - RGND = 2.5V
2.485 2.500 2.515 V
PWM OUTPUT
PWM Output Voltage LOW
Iload = ±500µA
-
-
0.3
V
PWM Output Voltage HIGH
Iload = ±500µA
4.0
-
-
V
DRIVER ENABLE OUTPUT
DRVEN Output Voltage LOW
DRVEN Output Voltage HIGH
Iload = ±1mA
Iload = ±1mA
-
-
0.3
V
4.0
-
-
V
SENSE CURRENT OUTPUT
Sensed Current Accuracy
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 80µA
77 86 95
µA
Overcurrent Trip Level
90 105 120 µA
Maximum voltage at IDROOP and IOUT
-
-
2
V
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
Undervoltage Offset From VID
I_PGOOD = 4mA
VSEN Falling
-
-
0.3
V
70 75 80 %VID
Overvoltage Threshold
Voltage above VID, After Soft Start (Note 4)
180 200 230 mV
Before Enable
1.45 1.5 1.55 V
VCC < POR Threshold
1.7 1.8 1.87 V
Overvoltage Reset Voltage
VCC ≥ POR Threshold, VSEN Falling
-
0.6
-
V
VCC < POR Threshold
-
1.5
-
V
OVP Drive Voltage
I_OVP = -10mA, VCC = 5V
3.0 3.6 5.0
V
NOTES:
3. When using the internal shunt regulator, VCC is clamped to 6.2V (max). Current must be limited to 25mA or less.
4. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
5. During soft-start, VDAC rises from 0 to VID. The overvoltage trip level is the higher of 1.5V and VDAC + 0.2V.
9
FN9156.2
December 27, 2004