ISL6564 Datasheet, PDF (22/27 Pages) Intersil Corporation – Multi-Phase PWM Controller with Linear 6-bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

ISL6564
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t₁ and the
approximated associated power loss is P_UP,1.
P _{U P,1}
≈
V_IN


I--_M---
N
+
-I-^P--2--^P--_



t--_1--


2_
f_S
(EQ. 16)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t₂. In Equation 17, the
approximate power loss is P_UP,2.
P_{UP, 2}
≈
V_IN


I--_M---
^N
–
I--_{P----P--}
2



t--_2--


2_
f_S
(EQ. 17)
A third component involves the lower MOSFET’s reverse-
recovery charge, Q_rr. Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q_rr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P_UP,3 and is approximately
P_UP,3 = V_IN Q_rr f_S
(EQ. 18)
Finally, the resistive part of the upper MOSFET’s is given in
Equation 18 as P_UP,4.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
P_UP,4 ≈ r_DS(ON)



-I-^M---
N
2
d
+
-I-^P----^P--²-
12
(EQ. 19)
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Current Sensing Resistor
The resistors connected between these pins and the
respective phase nodes determine the gains in the load-line
regulation loop and the channel-current balance loop as well
as setting the overcurrent trip point. Select values for these
resistors based on the room temperature r_DS(ON) of the
lower MOSFETs, DCR of inductor or additional resistor; the
full-load operating current, I_FL; and the number of phases, N
using Equation 20.
R_ISEN
=
7----0----R-×^{---1-X--0----–--6--}
I--_F----L-
N
(EQ. 20)
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistor. When the components of
one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled Channel-Current
Balance). Choose R_ISEN,2 in proportion to the desired
decrease in temperature rise in order to cause proportionally
less current to flow in the hotter phase.
R _{I S E N ,2}
=
R_ISEN
∆_-----T----2-
∆T₁
(EQ. 21)
In Equation 21, make sure that ∆T₂ is the desired temperature
rise above the ambient temperature, and ∆T₁ is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 21 is usually
sufficient, it may occasionally be necessary to adjust R_ISEN
two or more times to achieve optimal thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R_FB in Figure 8.
Its value depends on the desired full-load droop voltage
(V_DROOP in Figure 8). If Equation 20 is used to select each
ISEN resistor, the load-line regulation resistor is as shown in
Equation 22.
R_FB
=
-V----^D----^R----^O-----^O----^P--
70 ×10^–6
(EQ. 22)
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 21, the load-line regulation resistor
should be selected according to Equation 23 where I_FL is the
full-load operating current and R_ISEN(n) is the ISEN resistor
connected to the n^th ISEN pin.
∑ ^R_FB
=
----V-----^D----^R----^O-----^O----^P------
I_FL r_DS(ON)
R_ISEN(n)
n
(EQ. 23)
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
22
FN9156.2
December 27, 2004