ISL6564 Datasheet, PDF (18/27 Pages) Intersil Corporation – Multi-Phase PWM Controller with Linear 6-bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

ISL6564
2. The ISL6564 features an enable input (EN) for power
sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6564 in shutdown until the voltage at EN rises above
1.29V. The enable comparator has about 125mV of
hysteresis to prevent bounce. It is important that the
driver ICs reach their POR level before the ISL6564
becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6564 with the ISL66Xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on ENLL must be logic high to enable the
controller. This pin is typically connected to the
VID_PGOOD.
4. The VID code must not be 111111. This code signals the
controller that no load is present. The controller will enter
shut-down mode after receiving this code and will
execute soft-start upon receiving any other code. This
code can be used to enable or disable the controller but
it is not recommended. After receiving this code, the
controller executes a 2-cycle delay before changing the
overvoltage trip level to the shut-down level and disabling
PWM. Overvoltage shutdown can not be reset using this
code.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.29V;
For ISL6564CR, ENLL must be logic high; and VID cannot
be equal to 111111. When each of these conditions is true,
the controller immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed VID level as shown in Figure 11. The
PWM signals remain in the high-impedance state until the
controller detects that the ramping DAC level has reached
the pre-bias output-voltage level. This protects the system
against the large, negative inductor currents that would
otherwise occur when starting with a pre-existing charge on
the output as the controller attempted to regulate to zero
volts at the beginning of the soft-start cycle. The soft-start
time, t_SS, begins with a delay period equal to 64 switching
cycles followed by a linear ramp with a fixed rate at a speed
of 12.5mV/32µs.
t_SS = (2560)VID
(EQ. 13)
Equation 13 can be used to calculate the soft-start time. For
example, when VID is set to 1.2V, the soft-start time will be
3.072ms.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
VOUT, 500mV/DIV
EN, 5V/DIV
500µs/DIV
FIGURE 11. SOFT-START WAVEFORMS WITH AN UN-BIASED
OUTPUT
Fault Monitoring and Protection
The ISL6564 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 12
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
indication that the converter is operating after soft-start.
PGOOD pulls low during shutdown and releases high after a
successful soft-start. PGOOD will only transition low when
an undervoltage condition is detected or the controller is
disabled by a reset from EN, ENLL, POR, or one of the no-
CPU VID codes. After an undervoltage event, PGOOD will
return high unless the controller has been disabled. PGOOD
does not automatically transition low upon detection of an
overvoltage condition.
18
FN9156.2
December 27, 2004