ISL6564 Datasheet, PDF(17/27 Page) Intersil Corporation – Multi-Phase PWM Controller with Linear 6-bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

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ISL6564 Datasheet, PDF (17/27 Pages) Intersil Corporation – Multi-Phase PWM Controller with Linear 6-bit DAC Capable of Precision rDS(ON) or DCR Differential Current Sensing

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ISL6564

DYNAMIC

VID D/A

DAC

RREF

E/A

REF

VCC

GND

2.0V

0.5V

ROFS

OFS

ISL6564CR

VCC

GND

FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING

WITH ISL6564CR

Assuming the microprocessor controls the VID change at 1

bit every TVID, the relationship between the time constant of

RREF and CREF network and TVID is given by Equation 12.

CREF RREF = k TVID

(EQ. 12)

Where, TVID = 4Âµs, k is the number of the internal VID

change cycle. If Typically RREF is selected to be 1kâ¦, the

allowable delay time for VR to respond to new VID code is 5

VID change cycles (totally 20Âµs), the value of CREF should

be 22nF based on Equation 12.

Operation Initialization

Prior to converter initialization, proper conditions must exist

on the enable inputs and VCC. When the conditions are met,

the controller begins soft-start. Once the output voltage is

within the proper window of operation, PGOOD asserts

logic 1.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met before the ISL6564 is

released from shutdown mode.

Dynamic VID

Modern microprocessors need to make changes to their

core voltage as part of normal operation. They direct the

core-voltage regulator to do this by making changes to the

VID inputs during regulator operation. The power

management solution is required to monitor the DAC inputs

and respond to on-the-fly VID changes in a controlled

manner. Supervising the safe output voltage transition within

the DAC range of the processor without discontinuity or

disruption is a necessary function of the core-voltage

regulator.

The ISL6564 checks the VID inputs at the three edges of

16MHz clock. If the VID code is found to have changed, the

controller waits half of a complete cycle before executing a

12.5mV change. If during the half-cycle wait period, the

difference between DAC level and the new VID code

changes sign, no change is made. If the VID code is more

than 1 bit higher or lower than the DAC (not recommended),

the controller will execute step-up and step down VID

change at a speed of 12.5mV every 4Âµs until VID and DAC

are equal.

In order to ensure the smooth transition of output voltage

during VID change, a VID step change smoothing network

composed of RREF and CREF is required for an ISL6564

based voltage regulator. The selection of RREF is based on

the desired offset as detailed above in Output-Voltage Offset

Programming. The selection of CREF is based on the time

duration for 1 bit VID change and the allowable delay time.

ISL6564 INTERNAL CIRCUIT EXTERNAL CIRCUIT

POR

CIRCUIT

VCC

+12V

ENABLE

COMPARATOR

10.7kâ¦

1.40kâ¦

1.23V

SOFT START

AND

FAULT LOGIC

ENLL

FIGURE 10. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (EN) FUNCTION

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6564 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL6564 will not inadvertently turn off unless the bias

voltage drops substantially (see Electrical

Specifications).

FN9156.2

December 27, 2004

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