ISL6535 Datasheet, PDF (9/14 Pages) Intersil Corporation – Synchronous Buck Pulse-Width Modulator PWM Controller

ISL6535
Locate the ISL6535 within 2 to 3 inches of the MOSFETs, Q₁
and Q₂ (1 inch or less for 500kHz or higher operation). The
circuit traces for the MOSFETs’ gate and source connections
from the ISL6535 must be sized to handle up to 3A peak
current. Minimize any leakage current paths on the SS pin
and locate the capacitor C_ss close to the SS pin as the
internal current source is only 30µA. Provide local V_CC
decoupling between VCC and GND pins. Locate the
capacitor C_BOOT as close as practical to the BOOT pin and
the phase node.
C₂
R₂
C₁
COMP
FB
C₃
R₁
R₃
VOUT
ISL6535
FIGURE 6. COMPENSATION CONFIGURATION FOR THE
ISL6535 CIRCUIT
C₂
COMP
R₂
C₁
-
FB
E/A ⁺
VREF
R₃
C₃
R₁
GND
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_OUT
V_IN
UGATE
PHASE
LGATE
L
DCR
C
ESR
ISL6535 EXTERNAL CIRCUIT
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Compensating the Converter
The ISL6535 Single-phase converter is a voltage-mode
controller. This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 6).
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage is
regulated to the reference voltage level. The error amplifier
output is compared with the oscillator triangle wave to
provide a pulse-width modulated wave with an amplitude of
V_IN at the PHASE node. The PWM wave is smoothed by the
output filter. The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a
DC gain and shaped by the output filter, with a double pole
break frequency at F_LC and a zero at F_CE. For the purpose
of this analysis, L and DCR represent the output inductance
and its DCR, while C and ESR represents the total output
capacitance and its equivalent series resistance.
F_LC
=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE = ₂----_π-----_â‹---_C----¹--_â‹---_E----_S-----_R---
(EQ. 7)
The compensation network consists of the error amplifier
(internal to the ISL6535) and the external R₁ to R₃, C₁ to C₃
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of f_SW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R₁, R₂, R₃, C₁, C₂, and
C₃) in Figures 6 and 7. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R₁ (1kΩ to 10kΩ, typically). Calculate
value for R₂ for desired converter bandwidth (F₀). If
setting the output voltage to be equal to the reference set
voltage, as shown in Figure 7, the design procedure can
be followed as presented.
R₂ = -_D---^V-_M---^O--_A---^S-_X---^C--_â‹---_V^â‹---^R-_I--_N-¹----_â‹-^â‹--_F-^F---_L-⁰--_C---
(EQ. 8)
As the ISL6535 supports 100% duty cycle, D_MAX equals 1.
The ISL6535 uses a fixed ramp amplitude (V_OSC) of 1.9V,
Equation 8 simplifies to Equation 9:
R₂
=
-¹---^.--⁹----^â‹---^R-----¹----^â‹---^F----⁰--
V_IN ⋅ F_LC
(EQ. 9)
2. Calculate C₁ such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor in
Equation 10 to the desired number). The higher the quality
factor of the output filter and/or the higher the ratio F_CE/F_LC,
the lower the F_Z1 frequency (to maximize phase boost at
F_LC).
9
FN9255.1
May 5, 2008