ISL6535 Datasheet, PDF (10/14 Pages) Intersil Corporation – Synchronous Buck Pulse-Width Modulator PWM Controller

ISL6535
C₁
=
-----------------------¹-----------------------
2π ⋅ R₂ ⋅ 0.5 ⋅ F_LC
3. Calculate C₂ such that F_P1 is placed at F_CE.
C₂
=
-------------------------^C-----¹-------------------------
2π ⋅ R₂ ⋅ C₁ ⋅ F_CE – 1
(EQ. 10)
(EQ. 11)
4. Calculate R₃ such that F_Z2 is placed at F_LC. Calculate C₃
such that F_P2 is placed below f_SW (typically, 0.3 to 1.0
times f_SW). f_SW represents the switching frequency of the
regulator. Change the numerical factor (0.7) below to
reflect desired placement of this pole. Placement of F_P2
lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn reducing
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
R₃
=
-------^R-----¹--------
-^f--^S---^W----
F_LC
–
1
C₃
=
----------------------¹------------------------
2π ⋅ R₃ ⋅ 0.7 ⋅ f_SW
(EQ. 12)
It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^D----^M-----^A----^X-----^â‹---^V----^I--^N-- ⋅ -------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---^E-----^S----^R------^â‹---^C----------------------------------
V_{OSC 1 + s(f) ⋅ (ESR + DCR) ⋅ C + s}2_{(f) ⋅ L ⋅ C}
G_FB(f)
=
-----¹-----+-----^s---⁽---^f--⁾---^â‹---^R-----²----^â‹---^C-----¹------
s(f) ⋅ R₁ ⋅ (C₁ + C₂)
⋅
------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---⁽---^R----¹-----+-----^R----³----⁾---^â‹---^C-----³-------------------------------
(
1
+
s
(f)
⋅
R₃
⋅
C₃)
⋅
⎛
⎜
⎝
1
+
s
(f)
⋅
R₂
⋅
⎛
⎜
⎝
C^-C----₁^{-1---+-⋅---C-}C^----2-₂^-_{⎠⎟⎞}
⎞
⎟
⎠
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
(EQ. 13)
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1 = ₂----_π-----_â‹---_R--¹---₂----_â‹---_C-----₁-
F_P1
=
---------------------¹-----------------------
2π
⋅
R₂
⋅
-^C-----¹----^â‹---^C-----²--
C₁ + C₂
F_Z2 = ₂----_π-----_â‹---₍---_R----₁-----+¹----_R-----₃---₎----_â‹---_C----₃--
F_P2 = ₂----_π-----_â‹---_R--¹---₃----_â‹---_C-----₃-
(EQ. 14)
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previously mentioned guidelines
should yield a compensation gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 against the
capabilities of the error amplifier. The closed loop gain, G_CL, is
constructed on the log-log graph of Figure 8 by adding the
modulator gain, G_MOD (in dB), to the feedback
compensation gain, G_FB (in dB). This is equivalent to
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log
⎛
⎝
RR-----21--_⎠⎞
0
20log -^D----^M------^A----^X------^â‹---V----I---N--
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, f_SW.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
10
FN9255.1
May 5, 2008