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ISL6535 Datasheet, PDF (8/14 Pages) Intersil Corporation – Synchronous Buck Pulse-Width Modulator PWM Controller
ISL6535
The OCP trip point varies mainly due to MOSFET rDS(ON)
variations and layout noise concerns. To avoid overcurrent
tripping in the normal operating load range, find the ROCSET
resistor from the following equations with:
1. The maximum rDS(ON) at the highest junction
temperature
2. The minimum IOCSET from the specification table
Determine the overcurrent trip point greater than the
maximum output continuous current at maximum inductor
ripple current.
SIMPLE OCP EQUATION
ROCSET
=
I--O-----C----_---S----O----U---R----C----E-----•----r--D-----S----(--O----N----)
200 μ A
DETAILED OCP EQUATION
ROCSET
=
⎝⎛---I--O-----C----_---S---O----U----R----C----E-----+-----Δ--2-----I--⎠⎞----•-----r--D----S----(--O-----N----)
IHSOC • NU
NU = NUMBER OF HIGH SIDE MOSFETs
ΔI
=
-V----I--N-----------V----O----U-----T-
fSW • LOUT
•
V-----O----U----T--
VIN
fSW = Regulator Switching Frequency
(EQ. 6)
High Speed MOSFET Gate Driver
The integrated driver has the same drive capability and
feature as the Intersil’s 12V gate driver, ISL6612. The PWM
tri-state feature helps prevent a negative transient on the
output voltage when the output is being shut down. This
eliminates the Schottky diode that is used in some systems
for protecting the microprocessor from reversed-output-
voltage damage. See the ISL6612 datasheet FN9153 for
specification parameters that are not defined in the current
ISL6535 “Electrical Specifications” table on page 4.
Reference Input
The REFIN pin allows the user to bypass the internal 0.597V
reference with an external reference. If REFIN is NOT above
~2.2V, the external reference pin is used as the control
reference instead of the internal 0.597V reference. When not
using the external reference option, the REFIN pin should be
left floating. An internal 6µA pull-up keeps this REFIN pin
above 2.2V in this situation.
Internal Reference and System Accuracy
The Internal Reference is set to 0.597V. The total DC system
accuracy of the system is to be within 1.0% over commercial
temperature range and 1.5% over the industrial temperature
range. System Accuracy includes Error Amplifier offset, and
Reference Error. The use of REFIN may add up to 3mV of
offset error into the system (as the Error Amplifier offset is
trimmed out via the internal System reference).
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
A multi-layer printed circuit board is recommended. Figure 5
shows the critical components of the converter. Note that
capacitors CIN and COUT could each represent numerous
physical capacitors. Dedicate one solid layer (usually a middle
layer of the PC board) for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. Keep the
metal runs from the PHASE terminals to the output inductor
short. The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the
remaining printed circuit layers for small signal wiring.
VCC
PVCC
ISL6535
UGATE
BOOT
PHASE
LGATE
GND
SS
PGND
+12V
CBP_PVCC
CBP_VCC
VIN
CIN
Q1
CIN
LOUT
VOUT
COUT
Q2
CSS
KEY
TRACE SIZED FOR 3A PEAK CURRENT
SHORT TRACE, MINIMUM IMPEDANCE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 5. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
8
FN9255.1
May 5, 2008