ISL6532C Datasheet, PDF (9/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6532C
Figure 1 shows the soft start sequence for a typical cold
start. Due to the soft start capacitance, C_SS, on the
VREF_IN pin, the S5 to S0 transition profile of the V_TT rail
will have a more rounded features at the start and end of the
soft start whereas the V_DDQ profile has distinct starting and
ending points to the ramp up.
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals the ISL6532C can achieve PGOOD status
significantly faster than other devices that depend on
Latched_Backfeed_Cut for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532C will disable the V_TT linear regulator and the AGP
LDO controller. The V_DDQ standby regulator will be enabled
and the V_DDQ switching regulator will be disabled. NCH is
pulled low to disable the backfeed blocking MOSFET.
PGOOD will also transition LOW. When V_TT is disabled, the
internal reference for the V_TT regulator is internally shorted
to the V_TT rail. This allows the V_TT rail to float. When
floating, the voltage on the V_TT rail will depend on the
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V_TT rail may not bleed down to 0V.
The V_DDQ rail will be supported in the S3 state through the
standby V_DDQ LDO. When S3 transitions LOW, the Standby
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4 and 8µs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6532C will enable the V_DDQ switching regulator, disable
the V_DDQ standby regulator, enable the V_TT LDO and force
the NCH pin to a high impedance state turning on the
blocking MOSFET. The AGP LDO goes through a 2048 clock
cycle soft-start. The internal short between the V_TT
reference and the V_TT rail is released. Upon release of the
short, the capacitor on VREF_IN is then charged up through
the internal resistor divider network. The V_TT output will
follow this capacitor charge up, and acting as the S3 to S0
transition soft start for the V_TT rail. The PGOOD comparator
is enabled only after 2048 clock cycles, or typically 8.2ms,
have passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
should be noted that the soft start profile of the V_TT LDO
output will vary according to the value of the capacitor on the
VREF_IN pin.
S3
S5
V_{TT_FLOAT}
12VATX 2V/DIV
V_AGP
500mV/DIV
V_DDQ
500mV/DIV
V_TT
500mV/DIV
PGOOD
5V/DIV
12V POR
2048 CLOCK
CYCLES
PGOOD COMPARATOR
ENABLED
FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION
Active to Shutdown (S0 to S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6532C IC disables all
regulators and forces the PGOOD pin and the NCH pin LOW.
V_DDQ Over Current Protection (S0 State)
The over-current function protects the switching converter
from a shorted output by using the upper MOSFET on-
resistance, r_DS(ON), to monitor the current. This method
enhances the converter’s efficiency and reduces cost by
eliminating a current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R_OCSET)
programs the over-current trip level (see Typical Application
diagrams on pages 3 and 4). An internal 20µA (typical)
current sink develops a voltage across R_OCSET that is
referenced to the converter input voltage. When the voltage
across the upper MOSFET (also referenced to the converter
input voltage) exceeds the voltage across R_OCSET, the over-
current function initiates a soft-start sequence. The initiation
of soft start will affect all regulators. The V_TT regulator is
directly affected as it receives it’s reference from V_DDQ. The
AGP LDO will also be soft started, and as such, the AGP
LDO voltage will be disabled while the V_DDQ regulator is
disabled.
Figure 3 illustrates the protection feature responding to an
over current event. At time T0, an over current condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function
begins producing soft-start ramps. The delay interval seen
by the output is equivalent to three soft-start cycles. The
fourth internal soft-start cycle initiates a normal soft-start
ramp of the output, at time T1. The output is brought back
into regulation by time T2, as long as the over current event
has cleared.
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