ISL6532C Datasheet, PDF (8/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6532C
NCH (Pin 22)
NCH is an open-drain output that controls the MOSFET
blocking backfeed from V_DDQ to the input rail during sleep
states. A 2kΩ or larger resistor is to be tied between the 12V
rail and the NCH pin. Until the voltage on the NCH pin
reaches the NCH trip level, the PWM is disabled.
If NCH is not actively utilized, it still must be tied to the 12V
rail through a resistor. For systems using 5V dual as the
input to the switching regulator, a time constant, in the form
of a capacitor, can be added to the NCH pad to delay start of
the PWM switcher until the 5V dual has switched from
5VSBY to 5VATX.
PGOOD (Pin 21)
Power Good is an open-drain logic output that changes to a
logic low if any of the three regulators are out of regulation in
S0/S1/S2 state. PGOOD will always be low in any state other
than S0/S1/S2.
SLP_S5# (Pin 24)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 23)
This pin accepts the SLP_S3# sleep state signal.
FB2 (Pin 18)
Connect the output of the external linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V. This pin is monitored for under and
over-voltage events.
DRIVE2 (Pin 19)
Connect this pin to the gate terminal of an external N-
Channel MOSFET transistor. This pin provides the gate
voltage for the linear regulator pass transistor. It also
provides a means of compensating the error amplifier for
applications requiring the transient response of the linear
regulator to be optimized.
Functional Description
Overview
The ISL6532C provides complete control, drive, protection
and ACPI compliance for a regulator powering DDR memory
systems. It is primarily designed for computer applications
powered from an ATX power supply. A 250kHz Synchronous
Buck Regulator with a precision 0.8V reference provides the
proper Core voltage to the system memory of the computer.
An internal LDO regulator with the ability to both sink and
source current and an externally available buffered reference
that tracks the V_DDQ output by 50% provides the V_TT
termination voltage. The ISL6532C also features an LDO
regulator for 1.5V AGP Video and Core voltage.
ACPI compliance is realized through the SLP_S3 and
SLP_S5 sleep signals and through monitoring of the 12V
ATX bus.
Initialization
The ISL6532C automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors
the bias voltage at the 5VSBY and P12V pins. The POR
function initiates soft-start operation after the bias supply
voltages exceed their POR thresholds.
ACPI State Transitions
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, the ISL6532C receives its
bias voltage from the 5V Standby bus (5VSBY). As soon as
the SLP_S3 and SLP_S5 have transitioned HIGH, the
ISL6532C starts an internal counter. Following a cold start or
any subsequent S4/S5 state, state transitions are ignored
until the system enters S0/S1. None of the regulators will
begin the soft start procedure until the 5V Standby bus has
exceeded POR, the 12V bus has exceeded POR and V_NCH
has exceeded the trip level.
Once all of these conditions are met, the PWM error
amplifier will first be reset by internally shorting the COMP
pin to the FB pin. This reset lasts for 2048 clock cycles,
which is typically 8.2ms (one clock cycle = 1/f_OSC). The
digital soft start sequence will then begin.
The PWM error amplifier reference input is clamped to a
level proportional to the soft-start voltage. As the soft-start
voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output
capacitor(s). The internal VTT LDO will also soft start
through the reference that tracks the output of the PWM
regulator. The reference for the AGP LDO controller will rise
relative to the soft start reference. The soft start lasts for
2048 clock cycles, which is typically 8.2ms. This method
provides a rapid and controlled output voltage rise.
S3
S5
12VATX 2V/DIV
5VSBY
1V/DIV
V_DDQ
500mV/DIV
V_AGP
500mV/DIV
V_TT
500mV/DIV
PGOOD
5V/DIV
2048 CLOCK 2048 CLOCK
CYCLES
CYCLES
12V POR
SOFT START SOFT START ENDS
INITIATES PGOOD COMPARATOR
ENABLED
FIGURE 1. TYPICAL COLD START
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