ISL6532C Datasheet, PDF (10/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6532C
Had the cause of the over current still been present after the
delay interval, the over current condition would be sensed
and the regulator would be shut down again for another
delay interval of three soft start cycles. The resulting hiccup
mode style of protection would continue to repeat indefinitely.
V_DDQ
V_AGP
V_TT
500mV/DIV
INTERNAL SOFT-START FUNCTION
DELAY INTERVAL
T0
T1
T2
TIME
FIGURE 3. V_DDQ and V_TT OVER CURRENT PROTECTION
AND V_TT/V_AGP LDO UNDER VOLTAGE
PROTECTION RESPONSES
The over-current function will trip at a peak inductor current
(I_PEAK) determined by:
I_PEAK
=
I--_{O-----C----S----E----T-----x-----R-----O----C-----S----E---T--}
r_DS(ON)
where I_OCSET is the internal OCSET current source (20µA
typical). The OC trip point varies mainly due to the MOSFET
r_DS(ON) variations. To avoid over-current tripping in the
normal operating load range, find the R_OCSET resistor from
the equation above with:
1. The maximum r_DS(ON) at the highest junction
temperature.
2. The minimum I_OCSET from the specification table.
3. Determine I_PEAK for:
I_PEAK
>
I_OUT(MAX)
+
(_---∆_----I_---)
2
,
where
∆I
is
the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R_OCSET to smooth the voltage across R_OCSET in the
presence of switching noise on the input voltage.
V_TT Over Current Protection
The internal V_TT LDO is protected from fault conditions
through a 3.3A current limit. This current limit protects the
ISL6532C if the LDO is sinking or sourcing current. During
an overcurrent event on the V_TT LDO, only the V_TT LDO is
disabled. Once the over current condition on the V_TT rail is
removed, V_TT will recover.
Over/Under Voltage Protection
All three regulators are protected from faults through internal
Over/Under voltage detection circuitry. If the any rail falls
below 85% of the targeted voltage, then an undervoltage
event is tripped. An under voltage will disable all three
regulators for a period of 3 soft-start cycles, after which a
normal soft-start is initiated. If the output is still under 85% of
target, the regulators will continue to be disabled and soft-
started in a hiccup mode until the fault is cleared. This
protection feature works much the same as the VDDQ PWM
over current protection works. See Figure 3.
If the any rail exceeds 115% of the targeted voltage, then all
three outputs are immediately disabled. The ISL6532C will
not re-enable the outputs until either the bias voltage is
toggled in order to initiate a POR or the S5 signal is forced
LOW and then back to HIGH.
Thermal Protection (S0/S3 State)
If the ISL6532C IC junction temperature reaches a nominal
temperature of 140^oC, all regulators will be disabled. The
ISL6532C will not re-enable the outputs until the junction
temperature drops below 110^oC and either the bias voltage
is toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shoot-
through condition, the ISL6532C incorporates specialized
circuitry which insures that complementary MOSFETs are
not ON simultaneously.
The adaptive shoot-through protection utilized by the V_DDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
allowed to turned ON. This method allows the V_DDQ
regulator to both source and sink current.
Since the voltage of the MOSFET gates are being measured
to determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
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