ISL6532C Datasheet, PDF (12/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6532C
The PWM wave is smoothed by the output filter (L_O and C_O).
OSC
PWM
COMPARATOR
DRIVER
V_IN
L_O
V_DDQ
∆V_OSC
-
+
DRIVER
PHASE _CO
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₁
C₂
R₂
Z_FB
V_DDQ
Z_IN
C_{3 R3}
COMP
R₁
-
FB
+
R₄
ISL6532C
REFERENCE
V_DDQ
=
0.8
×



1
+
RR-----_{14-}
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
Modulator Break Frequency Equations
FLC=
---------------------¹---------------------
2π x LO x CO
FESR=
---------------------¹----------------------
2π x ESR x CO
The compensation network consists of the error amplifier
(internal to the ISL6532C) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R₁, R₂,
R₃, C₁, C₂, and C₃) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R₂/R₁) for desired converter bandwidth.
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC).
3. Place 2^ND Zero at Filter’s Double Pole.
4. Place 1^ST Pole at the ESR Zero.
5. Place 2^ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
F_Z1 = -₂---_π------x-----_R--¹--₂-----x------C----₂-
F_Z2
=
---------------------------¹---------------------------
2π x (R₁ + R₃) x C₃
F_P1
=
---------------------------¹-----------------------------
2π
x
R₂
x



C_{-C----11-----+x-----CC----2-2-}
F_P2
=
-----------------¹------------------
2π x R₃ x C₃
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
F_Z1 F_Z2 F_P1 F_P2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 ^(R2^/R1⁾
20LOG
0
(V_IN/∆V_OSC)
MODULATOR
-20
GAIN
-40
F_LC
F_ESR
-60
10
100
1K
10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This
LDO, which uses a MOSFET as the linear pass element,
requires feedback compensation to insure stability of the
system. The LDO requires compensation because of the
output impedance of the error amplifier.
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