ISL6529 Datasheet, PDF(9/19 Page) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

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ISL6529 Datasheet, PDF (9/19 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

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ISL6529, ISL6529A

+12V +5V

+3.3V

12VCC 5VCC

VOUT1

COUT1 +

LOUT

UGATE

ISL6529

LGATE ISL6529A

COMP

R2 C1

FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE PWM

However, since the value of R1 affects the values of the rest

of the compensation components, it is advisable to keep its

value less than 5kâ¦. Depending on the value chosen for R1,

R4 can be calculated based on the following equation:

R4 = V-----O-R---U--1--T---Ã-1---0-â---.-8-0---V.--8----V--

(EQ. 1)

If the output voltage desired is 0.8V, simply route VOUT1

back to the FB pin through R1, but do not populate R4.

The linear regulator output voltage is also set by means of

an external resistor divider as shown in Figure 5. The two

resistors used to set the output voltage should not exceed a

parallel equivalent value, referred to as RFB, of 5kâ¦. This

restriction is due to the manner of implementation of the soft-

start function. The following relationship must be met:

RFB

R-----5-----Ã-----R-----6-

R5 + R6

5kâ¦

(EQ. 2)

+3.3VIN

VOUT2

COUT2

DRIVE2

R12 C4

FB2

ISL6529

ISL6529A

To ensure the parallel combination of the feedback resistors

meets this criteria, choose a target value for RFB of less than

5kâ¦ and then apply the following equations:

V-----O----U----T----2-

VREF

RFB

(EQ. 3)

R6 = V-----O-R---U--5--T---Ã-2---V-â----R-V---E-R---F-E----F--

(EQ. 4)

where VOUT2 is the desired linear regulator output voltage

and VREF is the internal reference voltage, 0.8V. For an

output voltage of 0.8V, simply populate R5 with a value less

than 5kâ¦ and do not populate R6.

Converter Shutdown

Pulling and holding the FB2 pin above a typical threshold of

1.28V will shut down both regulators. Upon release of the

FB2 pin, the regulators enter into a soft-start cycle which

brings both outputs back into regulation.

PWM Controller Feedback Compensation

A simplified representation of the voltage-mode control loop

used for output regulation by the converter is shown in

Figure 6. The output voltage, VOUT, is fed back to the

negative input of the error amplifier which is regulated to the

reference voltage level, VREF. The error amplifier output,

VE/A, is compared with the triangle wave produced by the

oscillator, VOSC, to provide a pulse-width modulated (PWM)

signal from the PWM comparator. This signal is then used to

switch the MOSFET and produce a PWM waveform with an

amplitude of VIN at the PHASE node. The square-wave

PHASE voltage is then smoothed by the output filter, LOUT

and COUT, to produce a DC voltage level.

The modulator transfer function is defined as VOUT/VE/A.

The internal PWM comparator and driver circuits equate to a

DC gain block dominated by the supply voltage, VIN, divided

by the peak-to-peak magnitude of the triangle wave, âVOSC.

The output filter components, LOUT and COUT, shape the

overall modulator small-signal transfer function by

contributing a double pole break frequency at FLC and a

zero at FESR .

VOUT2 = 0.8 Ã ï£ï£«1 + RR-----56--ï£¸ï£¶

For frequency compensation considerations

set R5 to 4.64k and adjust R6 for the required voltage.

FIGURE 5. OUTPUT VOLTAGE SELECTION OF THE LINEAR

FN9070.5

April 12, 2005

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