ISL6529 Datasheet, PDF (10/19 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

ISL6529, ISL6529A
OSC
∆ V_OSC
PWM
COMP
-
+
Z_FB
DRIVER
V_IN
L_OUT
V_OUT
PHASE _{CO +}
ESR
(PARASITIC)
V_E/A
Z_IN
+ _VREF
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
ISL6529
-
FB
+
0.8V
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F_LC=
-------------------1--------------------
2π × L_O × C_O
(EQ. 5)
F_ESR= -2---_π-----_×-----E----S--1---R------_×----C-----_O---
(EQ. 6)
The compensation network consists of the error amplifier
and the impedance networks Z_IN and Z_FB. They provide the
link between the modulator transfer function and a
controllable closed loop transfer function of V_OUT/V_REF. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f_0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f_0dB and 180
degrees .
Compensation Break Frequency Equations
Poles:
F_P1
=
---------------------------1----------------------------
2
π
×
R₂
×


C-C----11-----+^{×-----CC-----22--}
F_P2 = _2----π-----_×-----R---1--3-----_×----C-----3--
(EQ. 8)
(EQ. 9)
Zeros:
F_Z1 = _2----π-----_×-----R---1--2-----_×----C-----1--
(EQ. 10)
F_Z2
=
---------------------------1---------------------------
2π × (R1 + R3) × C3
(EQ. 11)
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
1. Set the loop gain (R2/R1) to provide a converter
bandwidth of one quarter of the switching frequency.
2. Place the first compensation zero, F_Z1, below the output
filter double pole (~75% F_LC).
3. Position the second compensation zero, F_Z2, at the
output filter double pole, F_LC.
4. Locate the first compensation pole, F_P1, at the output
filter ESR zero, F_ESR.
5. Position the second compensation pole at half the
converter switching frequency, F_SW.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
INPUT VOLTAGE
ERROR
AMPLIFIER
INTERNAL 0.8V +
REFERENCE
-
DRIVE2
GATE
ISL6529
R12
FB
C16
C4
DRAIN
SIMPLIFIED MODEL
OF THE MOSFET
C_GD
1/gfs
SOURCE
X1
C_GS
R5
C_ISS = C_GS + C_GD
R6
R_SAMPLE
REGULATED OUTPUT
C_OUTPUT
ESR
R_LOAD
FIGURE 7. FIGURE A. SIMPLIFIED DIAGRAM OF THE LINEAR VOLTAGE REGULATOR
10
FN9070.5
April 12, 2005