ISL6529 Datasheet, PDF (6/19 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

ISL6529, ISL6529A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNITS
COMP Low Output, Sink Current
Undervoltage Level (V_FB/V_REF)
PWM CONTROLLER GATE DRIVERS
I_OUT Low
V_UV
2.5
3.5
-
mA
-
51.5
-
%
UGATE and LGATE Maximum Voltage
UGATE and LGATE Minimum Voltage
UGATE and LGATE Source Current
UGATE and LGATE Sink Current
UGATE and LGATE OUTPUT IMPEDANCE
LINEAR REGULATOR (DRIVE2)
V_HGATE
V_LGATE
I_GATE
I_GATE
R_DS(on)
12VCC = 12V
12VCC = 12V
12VCC = 12V
12VCC = 12V
12VCC = 12V
11
12
-
V
-
0
0.5
V
-
-1
-
A
-
1
-
A
-
3.1
4.3
Ω
DC Gain
Gain-Bandwidth Product
Slew Rate
FB2 Input Current
Drive2 High Output Voltage
Drive2 Low Output Voltage
Drive2 High Output Source Current
Drive2 Low Output Sink Current
Over-Voltage Level (V_FB2/V_REF)
Under-Voltage Level (V_FB2/V_REF)
REGULATOR ISOLATION
GBWP
SR
I_I 
V_OUT High
V_OUT Low
I_OUT High
I_OUT Low
V_OV
V_UV
R_L = 10K, C_L = 10pF
R_L = 10K, C_L = 10pF
R_L = 10K, C_L = 10pF
V_FB2 = 0.8V
Percent of Nominal
Percent of Nominal
-
80
-
dB
-
15
-
MHz
-
6
-
V/µs
-
20
150
nA
9.5
10.3
-
V
-
0.1
1.0
V
-0.7
-1.4
-
mA
0.85
1.2
-
mA
-
160
-
%
-
51.5
-
%
Change in Linear Regulator Output Voltage
∆Vout Linear Output = 2.5V, 6A Load Change on PWM -
<0.5
-
%
(Note 4)
Change in PWM Regulator Output Voltage
∆Vout PWM Output = 1.5V, 1A Load Change on Linear -
<0.5
-
%
(Note 4)
NOTE:
4. Measured in the evaluation board.
Functional Pin Descriptions
LGATE 1
PGND 2
GND 3
5VCC 4
DRIVE2 5
FB2 6
NC 7
14 UGATE
13 _12VCC
12 _NC
11 NC
10 COMP
9 FB
8 NC _{NC = NO INTERNAL}
CONNECTION
LGATE (Pin 1), (Pin 16 QFN)
Lower gate drive output. Connect to gate of the low-side
MOSFET.
PGND (Pin 2), (Pin 1 QFN)
This pin is the power ground return for the lower gate driver.
GND (Pin 3), (Pin 2 QFN)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Place via close to pin to minimize
impedance path to ground plane.
5VCC (Pin 4), (Pin 3 QFN)
Provide a well decoupled 5V bias supply for the IC to this
pin. The voltage at this pin is monitored for Power-On Reset
(POR) purposes.
DRIVE2 (Pin 5), (Pin 4 QFN)
Connect this pin to the gate terminal of an external
N-Channel MOSFET transistor. This pin provides the gate
voltage for the linear regulator pass transistor. It also
provides a means of compensating the error amplifier for
applications where the user needs to optimize the regulator
transient response.
6
FN9070.5
April 12, 2005