ISL6529 Datasheet, PDF (11/19 Pages) Intersil Corporation – Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller

ISL6529, ISL6529A
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20
log



V----V-O---I--S-N---C---_{}
60
40
COMPENSATION
GAIN
20
0
-20
20log


-^RR-----²¹--_
MODULATOR
-40
GAIN
F_LC F_ESR
LOOP GAIN
-60
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 8. Using the above
procedure should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW)
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Linear Regulator Compensation
The linear regulator in the ISL6529 is not internally
compensated and therefore allows the user to optimize
regulator performance with regard to transient load
response. Although the compensation network shown in the
application examples in this data sheet provide conservative
compensation for a variety of loads, performance can be
enhanced with attention to load requirements.
Low ESR capacitors can cause stability concerns in discrete
IC regulators. Even regulators that are internally
compensated can become unstable when these capacitors
are placed across their output. There have been suggestions
to add series resistance to these capacitors to stabilize the
regulator. This approach seems self defeating and throws
away a desirable quality.
Component Considerations
Many unsuspected poles and zeros develop with the
selection of external components and operating conditions
like output MOSFET transistors, output filter capacitors and
load current. These elements will be discussed beginning
with the influence of the MOSFET series output resistance,
the 1/gfs term shown in Figure 7. At low load currents and
low transconductance, the effective output resistance can be
as high as several kilohms. The low MOSFET gfs with
accompanying high series resistance and large values of
output capacitance form a low frequency pole that for many
cases becomes the dominate pole in the system and often
results in a stable no load system. As the load current is
increased, the MOSFET series output resistance is reduced
and moves the output pole into a higher frequency region,
adding phase shift that can result in a marginally stable or
unstable system.
Low output capacitor ESR can result in stability problems as
mentioned above. In contrast, high output capacitor ESR
can improve the system stability. The capacitor and its series
resistance function as a zero, often canceling other poles in
the loop. Figure 9 shows a system simulation with a 300µF,
100mΩ high ESR output capacitor. A single 10pF capacitor
from input to output of the error amplifier stabilizes the
system for load currents through the 1mA to 3A range.
80
60
40
3A
OUTPUT CAPACITOR
300µF, 100mΩ
20
1mA
55mA
0
BODE PLOT OF COMPENSATED REGULATOR AT 3 OUTPUT CURRENTS
0
-50 ^55mA
3A
-100
1mA
1mA
-150
-200
10
3A
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 9. LOOP RESPONSE WITH ONLY C16 = 10pF
COMPENSATION
Contrast this with Figure 10 that shows a Bode plot of
simulations of this regulator operating with a 100µF, 5mΩ
low ESR output capacitor. Note the phase approaching 180°
at high current. This is in contrast to the response previously
shown with the 300µF high ESR capacitor. The 300µF
output capacitor and its ESR provide phase lead to cancel or
offset the pole formed with the MOSFET output resistance
and 300µF capacitance. Also notice that system stability
varies widely with load current. A system can oscillate at no
load and be stable at full load, The converse is also possible.
Oscillation can also occur at load currents between the
current extremes.
11
FN9070.5
April 12, 2005