ISL6314 Datasheet, PDF (9/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
Functional Pin Description
VCC (Pin 18)
VCC is the bias supply for the ICs small-signal circuitry.
Connect this pin to a +5V supply and decouple using a
quality 0.1µF ceramic capacitor.
PVCC (Pin 19)
This pin is the power supply pin for the channel MOSFET
drivers, and can be connected to any voltage from +5V to
+12V depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0µF ceramic capacitor.
GND (Pin 33 = Metal Pad)
GND is the bias and reference ground for the IC, connected
to the metal pad under the IC.
EN (Pin 17)
This pin is a threshold-sensitive (approximately 0.85V) enable
input for the controller. Held low, this pin disables controller
operation. Pulled high, the pin enables the controller for
operation.
FS (Pin 3)
A resistor, R_T, tied to this pin sets the channel switching
frequency of the controller. Refer to Equation 42 for proper
resistor calculation.
The FS pin also controls whether the droop voltage (as
described under pins ISENO, ISEN-, ISEN+) is added to the
differential remote-sense amplifier’s output (VDIFF). Tying the
R_T resistor to ground connects droop voltage, allowing the
converter to incorporate output voltage droop proportional to
the output current. Tying the R_T resistor to VCC disconnects
the droop voltage.
VID0, VID1, VID2, VID3, VID4, VID5, VID6, and VID7
(Pins 31, 30, 29, 28, 27, 26, 25, 32)
These are the inputs for the internal DAC that provide the
reference voltage for output regulation. These pins respond to
TTL logic thresholds. These pins are internally pulled high, to
approximately 1.2V, by 40µA internal current sources for Intel
modes of operation, and pulled low by 20µA internal current
sources for AMD modes of operation. The internal pull-up
current decreases to 0 as the VID voltage approaches the
internal pull-up voltage. All VID pins are compatible with
external pull-up voltages not exceeding the IC’s bias voltage
(VCC).
VSEN (Pin 12)
This pin senses the microprocessor’s CORE voltage. Connect
this pin to the CORE voltage sense pin or point of the
microprocessor.
RGND (Pin 11)
This pin senses the local ground voltage of the
microprocessor. Connect this pin to the Ground sense pin or
point of the microprocessor.
FB and COMP (Pins 9, 7)
These pins are the internal error amplifier inverting input and
output respectively. The FB pin, COMP pin, and the VDIFF
pins are tied together through external R-C networks to
compensate the regulator.
DVC (Pin 8)
A series resistor and capacitor can be connected from the
DVC pin to the FB pin to compensate and smooth dynamic
VID transitions.
OCSET (Pin 13)
This is the overcurrent set pin. Placing a resistor from
OCSET pin to ISENO allows a 100µA current to flow out of
this pin, producing a voltage reference. Internal circuitry
compares the voltage at OCSET to the voltage at ISEN-, and
if ISEN- ever exceeds OCSET, the overcurrent protection
activates.
APA (Pin 6)
This is the Adaptive Phase Alignment set pin. A 100µA
current flows out the APA pin and by tying a resistor from this
pin to COMP the trip level for the Adaptive Phase Alignment
circuitry can be set.
REF (Pin 4)
The REF input pin is the positive input of the error amplifier. It
is internally connected to the DAC output through a 2kΩ
resistor. A capacitor is used between the REF pin and ground
to smooth the voltage transition during soft-start and Dynamic
VID transitions. This pin can also be returned to RGND if
desired.
NC (Pin 20)
This pin is presently NC (No Connect), but is reserved for a
future function.
OFS (Pin 5)
The OFS pin provides a means to program a DC current for
generating an offset voltage across the resistor between FB
and VDIFF. The offset current is generated via an external
resistor and precision internal voltage references. The polarity
is selected by connecting the resistor to GND (for positive
offset) or to VCC (for negative offset). For no offset, the OFS
pin should be left unconnected.
UGATE (Pin 23)
Connect this pin to the corresponding upper MOSFET gate.
This pin is used to control the upper MOSFET and is
monitored for shoot-through prevention purposes.
BOOT (Pin 22)
This pin provides the bias voltage for the upper MOSFET
drive. Connect this pin to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pin provides the necessary bootstrap charge.
9
FN6455.2
October 8, 2009