ISL6314 Datasheet, PDF (26/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
1. Choose an arbitrary value for C_COMP. The recommended
value is 0.01µF.
2. Plug the inductor L and DCR component values, and the
values for C_COMP chosen in Step 1, into Equation 30 to
calculate the value for R_COMP.
R_COMP
=
-------------------^L--------------------
DCR ⋅ C_COMP
(EQ. 30)
3. Use the new value for R_COMP obtained from
Equation 30, as well as the desired full load current, I_FL,
full load droop voltage, V_DROOP, and inductor DCR in
Equation 31 to calculate the value for R_S.
R_S
=
---------^I--^F---^L----------
V_DROOP
⋅
R_C
O
MP
⋅
D
CR
(EQ. 31)
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R₁ to match the time constants
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 19. Follow the
steps outlined in the following to ensure the R-C and
inductor L/DCR time constants are matched accurately.
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
2. Record ΔV1 and ΔV2 as shown in Figure 19.
3. Select new values, R_1,NEW, for the time constant resistor
based on the original value, R_1,OLD, using Equation 32.
R_{1, NEW}
=
R_1,
OLD
⋅
Δ_----V_----1--
ΔV₂
(EQ. 32)
4. Replace R₁ with the new value and check to see that the
error is corrected. Repeat the procedure if necessary.
ΔV₂
ΔV₁
V_OUT
I_TRAN
ΔI
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
Loadline Regulation Resistor
If loadline regulation is desired, the resistor on the FS pin,
R_T, should be connected to Ground (the value of R_T
separately selects the switching frequency, as per
Equation 42). The desired loadline, R_LL, can be calculated
by Equation 33 where V_DROOP is the desired droop voltage
at the full load current I_FL.
R_LL
=
V-----_{D----R----O-----O----P--}
I_FL
(EQ. 33)
Based on values for Equation 31, the desired loadline can
also be calculated from Equation 34.
R_LL
=
R-----_{C----O-----M----P------}⋅_{---D----C-----R---}
R_S
(EQ. 34)
If no loadline regulation is required, the resistor on the FS
pin, R_T, should be connected to the VCC pin (the value of
R_T separately selects the switching frequency, as per
Equation 42).
APA Pin Component Selection
A 100µA current flows out of the APA pin and across R_APA
to set the APA trip level. A 1000pF capacitor, C_APA, should
also be placed across the R_APA resistor to help with noise
immunity. An APA trip level of 500mV is recommended for
most applications. Use Equation 35 to set R_APA to get the
desired APA trip level.
R_APA
=
-^V----^A----^P----^A---^,---^T---^R-----^I-^P--
100 × 10^–6
=
-----⁵---⁰----⁰---^m------^V-------
100 × 10^–6
=
5kΩ
(EQ. 35)
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATION WITH LOAD-LINE REGULATION
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C, as shown in
Figure 20.
26
FN6455.2
October 8, 2009