ISL6314 Datasheet, PDF (28/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
ISL6314
VDIFF
FIGURE 21. COMPENSATION CIRCUIT WITHOUT LOAD-LINE
REGULATION
.
R₁
=
R_FB
⋅ ------------C------^â‹---E----S-----R-------------
L ⋅ C – C ⋅ ESR
C₁
=
-----L-----^â‹---C-----^–-----C------^â‹---E----S-----R--
R_FB
C₂
=
----------------------------------------------V-----^I--^N------------------------------------------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_P-P
R_C
=
-V----^P----^P-----^â‹---^⎝⎛---2----^π---^⎠⎞---²-----^â‹---f--⁰----^â‹---f--^H----^F-----^â‹---L-----^â‹---C-----^â‹---R-----^F----^B--
V_IN ^{⋅ (2 ⋅ π ⋅ f}_HF ^{⋅ L ⋅ C–1)}
(EQ. 37)
C_C
=
---------------V-----^I-^N------^â‹---⁽--2-----^â‹---^π-----^â‹---f--^H----^F-----^â‹-------L-----^â‹---C----^–----1---⁾----------------
(2 ⋅ π)² ⋅ f₀ ⋅ f_HF ⋅ ( L ⋅ C) ⋅ R_FB ⋅ V_P-P
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 37, R_FB is selected arbitrarily, typically in the 1kΩ
to 5kΩ range. The remaining compensation components are
then selected according to Equation 37.
In Equation 37, L is the filter inductance; C is the sum total of
all output capacitors; ESR is the equivalent-series resistance
of the bulk output-filter capacitance; and V_P-P is the
peak-to-peak sawtooth signal amplitude as described in the
“Electrical Specifications” on page 6.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase node. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductor
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with minimizing the cost of this part
of the circuit. The critical load parameters in choosing the
output capacitors are the maximum size of the load step, ΔI,
the load-current slew rate, di/dt, and the maximum allowable
output-voltage deviation under transient loading, ΔV_MAX.
Capacitors are characterized according to their capacitance,
ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, Equation 38 shows the output voltage initially
deviates by an amount as expressed in Equation 38:
ΔV ≈ ESL ⋅ -d---i + ESR ⋅ ΔI
dt
(EQ. 38)
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV_MAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see “Output Ripple”
on page 10 and Equation 39), a voltage develops across the
bulk capacitor ESR equal to I_{C(P-P )} (ESR). Thus, once the
output capacitors are selected, the maximum allowable
ripple voltage, V_P-P(MAX), determines the lower limit on the
inductance.
L
≥ ESR ⋅
⎛
⎝
V_IN
–
V_O
U
⎞
T_⎠
⋅
V_OUT
----------------------------------------------------------
f_S ⋅ V_IN ⋅ V_P-P(MAX)
(EQ. 39)
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductor must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV_MAX. This places an upper limit on inductance.
Equation 40 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 41
28
FN6455.2
October 8, 2009