ISL6314 Datasheet, PDF (25/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
.
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q ⋅ VCC
P _{Q g _Q1}
=
3_--
2
⋅
Q_G1
⋅
P
V
CC
⋅
F_S
W
⋅
N_Q
1
(EQ. 27)
P_{Qg_Q2} = Q_G2 ⋅ PVCC ⋅ F_SW ⋅ N_Q2
I_DR
=
⎛
⎝
3_--
2
⋅
Q_G
1
⋅
N
Q
1
+
Q_G2
⋅
N_{Q2⎠⎞}
⋅ F_SW + I_Q
(EQ. 28)
In Equations 27 and 28, P_{Qg_Q1} is the total upper gate drive
power loss and P_{Qg_Q2} is the total lower gate drive power
loss; the gate charge (Q_G1 and Q_G2) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I_Q is the driver total
quiescent current with no load at both drive outputs; N_Q1 and
N_Q2 are the number of upper and lower MOSFETs
respectively. The I_Q*VCC product is the quiescent power of
the controller without capacitive load and is typically 75mW at
300kHz.
PVCC
BOOT
R_HI1
R_LO1
PHASE
UGATE
C_GD
G
R_G1
R_GI1
C_GS
S
D
C_DS
Q1
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
R_HI2
R_LO2
LGATE
C_GD
G
R_G2
R_GI2
C_GS
S
D
C_DS
Q2
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P_{DR_UP}, the lower drive path resistance,
P_{DR_UP}, and in the boot strap diode, P_BOOT. The rest of the
power will be dissipated by the external gate resistors (R_G1
and R_G2) and the internal gate resistors (R_GI1 and R_GI2) of
the MOSFETs. Figures 16 and 17 show the typical upper and
lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P_DR, can be roughly
estimated as shown in Equation 29:
P_DR = P_{DR_UP} + P_{DR_LOW} + P_BOOT + (I_Q ⋅ VCC)
(EQ. 29)
P_BOOT
=
-^P----^Q----^g----^_--^Q-----¹-
3
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
-_R----_L---_O-----₁^R----+-^L---^O-_R----¹-_E----_X----_T---₁- _{⎠⎟⎞}
⋅
P_{-----Q----g----_--Q-----1-}
3
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^- _{⎠⎟⎞}
⋅ ^P-----^Q----^g----^_---^Q----²-
2
R_EXT1
=
R_G1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G2
+
R_{-----G-----I-2--}
N_Q2
Inductor DCR Current Sensing Component
Selection
For accurate load line regulation, the ISL6314 senses the
total output current by detecting the voltage across the
output inductor DCR (as described in “Load-Line (Droop)
Regulation” on page 16). As Figure 18 illustrates, an R-C
network is required to accurately sense the inductor DCR
voltage and convert this information into a “droop” voltage,
which is proportional to the total output current.
PHASE
V_L(s)
L
DCR
INDUCTOR
IL
R_S
I_OUT
V_OUT
C_OUT
ISEN-
ISENO
-
V_DROOP
+ ^ISEN+
C_COMP R_COMP
(OPTIONAL)
ISL6314
FIGURE 18. DCR SENSING CONFIGURATION
Choosing the components for this current sense network is a
two step process. First, R_COMP and C_COMP must be
chosen so that the time constant of this R_COMP - C_COMP
network matches the time constant of the inductor L/DCR.
Then the resistor R_S must be chosen to set the current
sense network gain, obtaining the desired full load droop
voltage. Follow the steps outlined in the following to choose
the component values for this R-C network.
25
FN6455.2
October 8, 2009