ISL54105 Datasheet, PDF (9/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105
Application Information
The ISL54105 is a TMDS regenerator, locking to the incoming
DVI or HDMI signal with triple Clock Data Recovery units
(CDRs) and a Phase Locked Loop (PLL). The PLL generates a
low jitter pixel clock from the incoming TMDS clock. The TMDS
data signals are equalized, sliced by the CDR, re-aligned to the
PLL clock, and sent out the TMDS outputs.
Activity Detection
The TMDS input is considered active using one of two
methods. The original default activity detect method (register
0x03b4 = 1) is to measure the common mode of the TMDS
clock input for each channel. If the common mode is 3.3V, it
indicates that there is nothing connected to that input, or that
whatever is connected is turned off (inactive). This has been
found to be relatively unreliable, particularly with weak signals.
The preferred method of activity detection is looking for an
active AC signal on the TMDS clock input for that channel
(register 0x03b4 = 1). This is more robust, however
disconnected inputs will cause both inputs to the differential
receiver to be the same level - 3.3V. If the offset error of the
differential TMDS receiver is very small, the receiver can not
resolve a 1 or a 0 and will randomly switch between states,
which may be detected as an active clock. Register 0x03 bits
5 and 6 allow a 10mV or 20mV offset to be added to the input
stage of the clock inputs, eliminating this problem. This offset
will slightly reduce the sensitivity of TMDS receiver for the
clock lines, but since the clock signals are much lower
frequency than the data, they will not be nearly as
attenuated, so this is not a problem in practice.
Again, using the AC activity detection method (register
0x03b4 = 0) is recommended.
Rx Equalization
Register 0x08 bits 3:0 control the amount of equalization
applied to the TMDS inputs, providing 4 bits of control. The
equalization range available is from a minimum of 1dB boost
to a maximum of 13dB at 800MHz, in 0.8dB increments.
Ideally, the equalization is adjusted in the final application to
provide optimal performance with the specific DVI/HDMI
transmitter and cable used. In general, the amount of
equalization required is proportional to the cable length. If
the equalization must be fixed (can not be adjusted in the
final application), an equalization setting of 0xA works well
with short cables as well as medium to longer cables.
Tx Pre-emphasis
The transmit pre-emphasis function sinks additional current
during the first bit after every transition, increasing the slew
rate for a given capacitance, and helping to maintain the
slew rate when using longer/higher capacitance cables.
Pre-emphasis is controlled by register 0x06 bits 7:4, and
ranges from a minimum of 0mA (no pre-emphasis) to
1.875mA (max pre-emphasis).
PLL Bandwidth
The 2-bit PLL Bandwidth register controls the loop
bandwidth of the PLL used to recover the incoming clock
signal. The default 4MHz setting works well in most
applications, however a lower bandwidth of 1MHz has
proven to work just as well with good TMDS sources and
slightly better with marginal sources.
Power-down
The chip can be placed in a Power-down mode when not in
use to conserve power. Setting the Power-down bit (register
0x02 bit 5) to a 1 or pulling the PD input pin high places the
chip in a minimal power consumption mode, turning off all
TMDS outputs and disconnecting all TMDS inputs. Serial I/O
stays operational in PD mode. Note that the PD pin must be
low during power-on in order to initialize the I²C interface.
Note: When exiting Power-down, a termination resistor
Recalibration cycle must be run to re-trim the termination
resistors (see register 0x03[7]).
Typical Performance
Setup A (Figure 2) was used to capture the TMDS eye
diagrams shown in Figure 3 and Figure 4:
CHROMA 2326
VIDEO PATTERN
GENERATOR @
UXGA 60Hz
15m DUAL-LINK
DVI CABLE
DELL 2000FP
UXGA MONITOR
FIGURE 3
FIGURE 4
FIGURE 2. TEST SETUP A
The 162.5Mpixel/s (UXGA 60Hz) DVI output of the Chroma
2326 was terminated into a TPA2 Plug adapter and
measured with a LeCroy differential probe and 6MHz SDA
using the LeCroy’s software clock recovery. As Figure 3
shows, the amplitude of the TMDS signal is slightly low, but
the eye is otherwise acceptable.
FIGURE 3. EYE DIAGRAM AT OUTPUT OF CHROMA
GENERATOR
9
FN6723.0
June 11, 2008