ISL54105 Datasheet, PDF (7/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE)
0x04
Termination Control (0x00)
0x05
Output Options (0x00)
0x06
Data Output Drive (0x00)
0x07
0x08
Reserved (0xCC)
Equalization (0xCC)
0x09
Test Pattern Generator (0x00)
BIT(S) FUNCTION NAME
DESCRIPTION
1:0 Reserved
Set to 00.
2 Data Termination
0: TMDS Data inputs terminated into 50Ω (normal
operation)
1: TMDS Data inputs terminated into 100Ω (for paralleled
inputs)
5:3 Reserved
Set to 000.
6 Clk Termination
0: TMDS Clock inputs terminated into 50Ω (normal
operation)
1: TMDS Clock inputs terminated into 100Ω (for paralleled
inputs)
7 Reserved
Set to 0.
0 Tri-state Clock
Outputs
0: Normal Operation
1: Clock outputs tri-stated (allows another chip to drive the
output clock pins)
1 Tri-state Data
Outputs
0: Normal Operation
1: Data outputs tri-stated (allows another chip to drive the
output data pins)
2 Invert Output
Polarity
0: Normal Operation
1: The polarity of the TMDS data outputs is inverted
(+ becomes -, - becomes +). TMDS clock unchanged.
3 Reverse Output
Order
0: Normal Operation
1: CH0 data is output on CH2 and CH2 data is output on
CH0. No change to CH1.
3:0 Transmit Current
Transmit Drive Current for data signals, adjustable in
0.125mA steps. Clock current is fixed at 10mA.
0x0: 10mA
0x8: 11mA
0xF: 11.875mA
7:4 Transmit
Pre-emphasis
Drive boost (in 0.125mA steps) added during first half of
each bit period for data signals. Clock signals do not have
pre-emphasis.
0x0: 0mA
0x8: 1mA
0xF: 1.875mA
7:0 Reserved
Default value of 0xCC is OK, can also be set to 0x00.
3:0 Equalizer Gain
Boost (dB) = 1dB + <gain value> * 0.8dB
0x0: 1dB boost at 800MHz
0xC: 10.6dB boost at 800MHz (default)
0xF: 13dB boost at 800MHz
7:4 Reserved
Default value of 0xC is OK, can also be set to 0x0.
1:0 Generator Mode
When a 25MHz to 165MHz clock is applied to the clock
input, this function will output a PRBS7 pattern on the TX
pins.
0: Normal operation (test patterns disabled)
1: PRBS7 pattern
2: Low frequency toggle (0000011111…)
3: High frequency toggle (1010101010…)
Note: When switching from the high frequency toggle
pattern to the low frequency toggle pattern, you must first
select normal operation.
2 Enable PRBS7 Error Enables PRBS7 error counter in registers 0x0A to 0x0C.
Counter
0: Disable PRBS7 Error Counter
1: Enable PRBS7 Error Counter
7
FN6723.0
June 11, 2008