ISL54105 Datasheet, PDF (11/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105
drawing current from the external TMDS receiver it is
attached to.
3.3V_TX
V_D
3.3V_RX
Rx_N
50
V_D_ESD ^{(41, 53)}
Tx
Tx_N
ISL54105
FIGURE 8. ISL54105 ESD PROTECTION DIODES
This is non-ideal and can cause the ISL54105 to fail HDMI
Compliance Test 7-3 (“V_OFF”). V_OFF is the voltage across
each 50Ω Rx_N resistor when the power is removed from the
device containing the ISL54105.
Modifying the PCB layout per Figure 9 to add a Schottky
diode between the V_D power net and the V_D_ESD pins,
eliminates current flow from the ESD bus into V_D. This
reduces the amount of current drawn from the Tx supply, but
there is still some circuitry attached to the internal ESD bus
that will sink some current. So the current drawn from Rx will
be lower than if the diode were not there (reducing the V_OFF
magnitude), but still not low enough to pass Test 7-3.
3.3V_TX
V_D
D₁
V_D_ESD
C₁
0.1μF
(41, 53)
Tx
3.3V_RX
Rx_N
50
Tx_N
ISL54105
FIGURE 9. SCHOTTKY DIODE MODIFICATION
Intersil is currently sampling the ISL54105A, which is fully
compliant with Test 7-3 when applied using the circuit shown
in Figure 9. The ISL54105A is 100% drop-in and backwards
compatible with the ISL54105.
Using the ISL54105A in a layout designed for the ISL54105
(Figure 8) will result in the same behavior as the original
version. See Table 1 for the full matrix.
TABLE 1. VERSION/LAYOUT MATRIX
VERSION
FIGURE 8
FIGURE 9
ISL54105
Fails 7-3
Fails 7-3 (not as badly)
ISL54105A
Fails 7-3
Passes 7-3
Intersil recommends adding the Schottky circuit to all
designs to reduce Rx current drain in systems using the
original version and completely eliminate it in systems using
the ISL54105A.
Inter-Pair (Channel-to-Channel) Skew
The read pointers for Channel 0, 1, and 2 of the FIFO that
follows the CDR all have the same clock, so all 3 channels
transition within a few picoseconds of each other - there is
essentially no skew between the transitions of the three
channels.
However the FIFO read pointers may be positioned up to 2
bits apart relative to each other, introducing a random, fixed
channel-to-channel skew of skew of 1 or (much less
frequently) 2 bits. The random skew is introduced whenever
there is a discontinuity in the input signal (typically a video
mode change or a new mux channel selection). After the
CDRs and PLL lock, the skew is fixed until the next
discontinuity. This adds up to 2 bits of skew in addition to any
incoming skew, as shown in the following examples.
Figure 10 shows an input (the top three signals) with
essentially no skew. After the ISL54105 locks on to the
signal, there may be 1 bit of skew on the output, as shown in
Figure 10.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
INPUT SKEW
(none, in this Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
example)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 B
OUTPUT SKEW
(1 bit – 615ps at Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
162.5Mpixels/s)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 B
FIGURE 10. MAXIMUM ADDITIONAL INTERCHANNEL SKEW
FOR INPUTS WITH NO OR LITTLE SKEW
When there is pre-existing skew on the input, the ISL54105
can add up to 2 bits to the channel-to-channel skew. In the
example in Figure 11, the incoming red channel has 2.3 bits
11
FN6723.0
June 11, 2008