ISL54105 Datasheet, PDF (14/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105
SCL FROM
HOST
1
DATA OUTPUT
FROM TRANSMITTER
8
9
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 15. ACKNOWLEDGE RESPONSE FROM RECEIVER
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 16. VALID DATA CHANGES ON THE SDA BUS
START Command
ISL54105 Serial Bus
ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
A7
A6
A5
A4
A3
A2
A1
D7
D6
D5
D4
D3
D2
D1
(Repeat if desired)
R/W
0
A0
D0
Signals the beginning of serial I/O
ISL54105 Device Select Address Write
The first 7 bits of the first byte select the ISL54105 on the 2-wire
bus at the address set by the ADDR[6:0} pins. The R/W bit is a
0, indicating that the next transaction will be a write.
ISL54105 Register Address Write
This is the address of the ISL54105’s configuration register that
the following byte will be written to.
ISL54105 Register Data Write(s)
This is the data to be written to the ISL54105’s configuration register.
Note: The ISL54105’s Configuration Register’s address pointer auto
increments after each data write: repeat this step to write multiple
sequential bytes of data to the Configuration Register.
Signals from
the Host
SDA Bus
Signals from
the ISL54105
STOP Command
Signals the ending of serial I/O
S
T _{Serial Bus}
A
R
Address
T
Register
Address
Data
Write*
S
T ^{* The data write step may be repeated to write to the}
O ISL54105’s Configuration Register sequentially, beginning at
P _{the Register Address written in the previous step.}
a a a a a a a 0 AAAAAAAA d d d d d d d d
A
A
A
C
C
C
K
K
K
FIGURE 17. CONFIGURATION REGISTER WRITE
14
FN6723.0
June 11, 2008