ISL54105 Datasheet, PDF (8/16 Pages) Intersil Corporation – TMDS Regenerator

ISL54105
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME
DESCRIPTION
0x0A
PRBS7 Error Counter Link 0 (read only) 7:0 PRBS7 Error
Counter Link 0
PRBS7 Error Counter of Link 0. Saturates at 0xFF. Reading
this register clears this register at end of read
0x0B
PRBS7 Error Counter Link 1 (read only) 7:0 PRBS7 Error
Counter Link 1
PRBS7 Error Counter of Link 1. Saturates at 0xFF. Reading
this register clears this register at end of read
0x0C
PRBS7 Error Counter Link 2 (read only) 7:0 PRBS7 Error
Counter Link 2
PRBS7 Error Counter of Link 2. Saturates at 0xFF. Reading
this register clears this register at end of read
0x10
PLL Bandwidth (0x10)
Recommended default: 0x12
1:0 PLL Bandwidth
Selects between 4 PLL bandwidth settings
0: 4MHz (silicon default)
1: 2MHz
2: 1MHz (recommended default)
3: 500kHz
1MHz provides slightly better performance with high jitter/
high noise signals.
7:2 Reserved
Keep set to 000100 binary.
8
FN6723.0
June 11, 2008