ISL12032 Datasheet, PDF (9/26 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up

ISL12032
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action. It is an open drain active LOW output.
F_OUT (Frequency Output)
This pin outputs a clock signal, which is related to the crystal
frequency. The frequency output is user selectable and
enabled via the I²C bus. The options include seven different
frequencies or disable. It is a CMOS output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
VBAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be OR’ed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I²C interface speeds. It is disabled
when the backup power supply on the VBAT pin is activated.
V_DD, GND
Chip power supply and ground pins. The device will operate
with a power supply from V_DD = 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the V_DD pin to ground.
Functional Description
Power Control Operation
The power control circuit accepts a V_DD and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
the ISL12032 for up to 10 years. Another option is to use a
Super Capacitor for applications where V_DD is interrupted
for up to a month. See the “Application Section” on page 24
for more information.
Normal Mode (V_DD) to Battery Backup Mode
(VBAT)
To transition from the V_DD to VBAT mode, both of the
following conditions must be met:
Condition 1:
V_DD < VBAT - V_BATHYS
where V_BATHYS ≈ 50mV
Condition 2:
V_DD < V_TRIP
where V_TRIP ≈ 2.2V
Battery Backup Mode (VBAT) to Normal Mode
(V_DD)
The ISL12032 device will switch from the VBAT to V_DD
mode when one of the following conditions occurs:
Condition 1:
V_DD > VBAT + V_BATHYS
where V_BATHYS ≈ 50mV
Condition 2:
V_DD > V_TRIP + V_TRIPHYS
where V_TRIPHYS ≈ 30mV
These power control situations are illustrated in Figures 3
and Figure 4.
V_DD
V_TRIP
VBAT
VBAT - V_BATHYS
BATTERY BACKUP
MODE
2.2V
1.8V
VBAT + V_BATHYS
FIGURE 3. BATTERY SWITCHOVER WHEN VBAT < V_TRIP
V_DD
VBAT
V_TRIP
V_TRIP
BATTERY BACKUP
MODE
3.0V
2.2V
V_TRIP + V_TRIPHYS
FIGURE 4. BATTERY SWITCHOVER WHEN VBAT > V_TRIP
The I²C bus is normally deactivated in battery backup mode
to reduce power consumption, but can be enabled by setting
the I²CBAT bit. All the other inputs and outputs of the
ISL12032 are active during battery backup mode unless
disabled via the control register.
Power Failure Detection
The ISL12032 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
power to the device (both V_DD and VBAT very near
0.0VDC). Note that in cases where the VBAT input is at 0.0V
and the V_DD input dips to <1.8V, then recovers to normal
level, the SRAM registers may not retain their values
(corrupted bits or bytes may result).
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FN6618.2
April 16, 2009