ISL12032 Datasheet, PDF (19/26 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up

ISL12032
ACFP = 11b (10 total AC cycles)
So the resulting crystal cycle count must be within:
±(10 AC cycles x 2 crystal cycles/AC cycle) or
± 20 total crystal cycles (error budget) as shown in Table 23.
TABLE 23. AC/CRYSTAL FREQUENCY FAILURE CRITERION
ACFC1 ACFC0
CRITERION
TOTAL XTAL
CYCLE ERROR
BUDGET
0
0 1 crystal cycle per AC cycle ACFP x 1
0
1 2 crystal cycle per AC cycle ACFP x 2
1
0 1 crystal cycle in all AC
1
cycles
1
1 2 crystal cycles in all AC
2
cycles
Fine Trim Compensation Register (FTR)
This register (Table 24) provides control of the crystal
oscillator clock compensation and the AC clock input
minimum level detect.
TABLE 24. FINE TRIM COMPENSATION REGISTER
ADDR 7 6
14h X X
5
4
3
2
1
0
X ACMIN XDTR3 XDTR2 XDTR1 XDTR0
AC MINIMUM (ACMIN)
This bit determines the minimum peak-to-peak voltage level
for the AC clock input as a percentage of the existing V_DD
supply. ACMIN = 0 sets the minimum level to 5% x V_DD.
ACMIN = 1 sets the minimum level to 10% x V_DD.
DIGITAL TRIM REGISTER (XDTR<3:0>)
The digital trim register bits control the amount of trim used
to adjust for the crystal clock error. This trim is accomplished
by adding or subtracting the 32kHz clock in the clock counter
chain to adjust the RTC clock. Calibration can be done by
monitoring the F_OUT pin with a frequency counter with the
frequency output set to 1.0Hz, with no AC input.
TABLE 25. XDTR FREQUENCY COMPENSATION
XDTR3
XDTR2
XDTR1
FREQUENCY
COMPENSATION
XDTR0
(ppm)
0
0
0
0
0
0
0
0
1
10
0
0
1
0
20
0
0
1
1
30
0
1
0
0
40
0
1
0
1
50
0
1
1
0
60
0
1
1
1
0
1
0
0
0
0
1
0
0
1
-10
1
0
1
0
-20
1
0
1
1
-30
1
1
0
0
-40
1
1
0
1
-50
1
1
1
0
-60
1
1
1
1
0
DST Control Registers (DSTCR)
8 bytes of control registers have been assigned for the
Daylight Savings Time (DST) functions. DST beginning (set
Forward) time is controlled by the registers DstMoFd,
DstDwFd, DstDtFd, and DstHrFd. DST ending time (set
Backward or Reverse) is controlled by DstMoRv, DstDwRv,
DstDtRv and DstHrRv.
Tables 26 and 27 describe the structure and functions of the
DSTCR.
DST FORWARD REGISTERS (15H TO 18H)
DSTE is the DST Enabling Bit located in bit 7 of register 15h
(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.
Upon powering up for the first time (including battery), the
DSTE bit defaults to “0”.
DST forward is controlled by the following DST Registers:
DstMoFd sets the Month that DST starts. The default value
for the DST begin month is April (04h).
DstDwFd sets the Day of the Week that DST starts.
DstDwFdE sets the priority of the Day of the Week over the
Date. For DstDwFdE=1, Day of the week is the priority. Note
that Day of the week counts from 0 to 6, like the RTC
registers. The default for the DST Forward Day of the Week
is Sunday (00h).
DstDtfd controls which Date DST begins. The default value
for DST forward date is on the first date of the month (01h).
DstDtFd is only effective if DstDwFdE = 0.
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FN6618.2
April 16, 2009