ISL12032 Datasheet, PDF (21/26 Pages) Intersil Corporation – Low Power RTC with Battery Backed SRAM and 50/60 Cycle AC Input and Xtal Back-up

ISL12032
Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30am.
• Set Alarm registers as follows:
BIT
ALARM
REGISTER 7 6 5 4 3 2 1 0 HEX DESCRIPTION
SCA0 0 0 0 0 0 0 0 0 00h Seconds disabled
MNA0 1 0 1 1 0 0 0 0 B0h Minutes set to 30,
enabled
HRA0 1 0 0 1 0 0 0 1 91h Hours set to 11,
enabled
DTA0
1 0 0 0 0 0 0 1 81h Date set to 1,
enabled
MOA0 1 0 0 0 0 0 0 1 81h Month set to 1,
enabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week
disabled
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
Example 2
• Pulsed interrupt once per minute (IM = ”1”)
• Interrupts at one minute intervals when the seconds
register is at 30 seconds.
• Set Alarm registers as follows:
BIT
ALARM
REGISTER 7 6 5 4 3 2 1 0 HEX
DESCRIPTION
SCA0
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
enabled
MNA0 0 0 0 0 0 0 0 0 00h Minutes disabled
HRA0 0 0 0 0 0 0 0 0 00h Hours disabled
DTA0 0 0 0 0 0 0 0 0 00h Date disabled
MOA0 0 0 0 0 0 0 0 0 00h Month disabled
DWA0 0 0 0 0 0 0 0 0 00h Day of week disabled
Once the registers are set, the following waveform will be
seen at IRQ:
RTC AND ALARM REGISTERS ARE BOTH “30s”
60s
FIGURE 5. IRQ WAVEFORM
Note that the status register ALM0 bit will be set each time
the alarm is triggered, but does not need to be read or
cleared.
Time Stamp V_DD to Battery Registers (TSV2B)
The TSV2B section bytes are identical to the RTC register
section, except they do not extend beyond the Month. The
Time Stamp captures the FIRST V_DD to Battery Voltage
transition time, and will not update upon subsequent events,
until cleared (only the first event is captured before clearing).
Set CLRTS = 1 to clear this register (Addr 11h, PWRVDD
register).
Time Stamp Battery to V_DD Registers (TSB2V)
The Time Stamp Battery to V_DD section bytes are identical
to the RTC section bytes, except they do not extend beyond
Month. The Time Stamp captures the LAST transition of
VBAT to V_DD (only the last power up event of a series of
power up/down events is retained). Set CLRTS = 1 to clear
this register (Addr 11h, PWRVDD register).
Time Stamp Event Registers (TSEVT)
The TSEVT section bytes are identical to the RTC section
bytes, except they do not extend beyond the Month. The Time
Stamp captures the first event and the most recent three
events. The first event Time Stamp will not update until cleared.
All 4 Time Stamps are all cleared to “0” when writing the event
counter (0Bh) is set to “0”.
Note: The time stamp registers are cleared to all “0”,
including the month and day, which is different from the RTC
and alarm registers (those registers default to 01h). This is
the indicator that no time stamping has occurred since the
last clear or initial power-up. Once a time stamp occurs,
there will be a non-zero time stamp.
User Memory Registers (accessed by
using Slave Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
Writes to this section do not need to be proceeded by setting
the WRTC bit.
I²C Serial Interface
The ISL12032 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12032 operates as a slave device in all applications.
All communication over the I²C interface is conducted by
sending the MSB of each byte of data first.
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FN6618.2
April 16, 2009