X9521 Datasheet, PDF (8/25 Pages) Xicor Inc. – Dual DCP, EEPROM Memory

X9521
Signals from
the Master
SDA Bus
Signals from
the Slave
WRITE Operation
READ Operation
S
S
t
a
r
Slave
Address
Instruction
Byte
t
a
r
Slave
Address
S
t
Data Byte o
t
t
p
10101110
W
T
00000
P
1
P
0
10101111
A
A
A
C
C
C
K
K
K
“Dummy” write
Figure 10. DCP Read Sequence
DCPx
-
x=1
MSB
LSB
“-” = DON’T CARE
x=2
P0 = 0) or (P1 = 1, P0 = 1) are reserved sequences, and
will result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” R_WX (x=1,2) at the
“lowest” tap position, Therefore, the resistance between
R_WX and R_LX is a minimum (essentially only the Wiper
Resistance, R_W).
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9521 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1 - P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9521.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9521
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
Signals from
the Master
S
t
WRITE Operation
a
r
Slave
Address
t _Address
Byte
S
t
Data
o
Byte
p
SDA Bus
101 00 000
Signals from
the Slave
A
A
A
Internal _C
C
C
Device
Address
K
K
K
Figure 11. EEPROM Byte Write Sequence
8
FN8207.1
August 25, 2005