X9521 Datasheet, PDF (2/25 Pages) Xicor Inc. – Dual DCP, EEPROM Memory

PIN CONFIGURATION
X9521
R_H2
R_W2
R_L2
NC
NC
NC
WP
SCL
SDA
V_SS
20 Pin TSSOP
1 20
2 19
3
18
4
17
5
16
6
15
7
14
8
13
9 12
10 11
Vcc
NC
NC
NC
NC
NC
NC
R_H1
R_W1
R_L1
PIN ASSIGNMENT
Pin
Name
1
R_H2
2
R_w2
3
R_L2
7
WP
8
9
10
11
12
13
20
4, 5, 6,
14, 15,
16, 17,
18, 19
SCL
SDA
Vss
R_L1
R_w1
R_H1
Vcc
NC
Function
Connection to end of resistor array for (the 256 Tap) DCP 2.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP2.
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write Pro-
tection is enabled, and the device Block Lock feature is active (i.e. the Block Lock bits are NOT [0,0]), then
no “write” (volatile or nonvolatile) operations can be performed in the device (including the wiper position
of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an internal “pull-
down” resistor, thus if left floating the write protection feature is disabled.
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the de-
vice. The SDA pin input buffer is always active (not gated). This pin requires an external pull up resistor.
Ground.
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
Connection to end of resistor array for (the 100 Tap) DCP 1.
Supply Voltage.
No connect.
SCL
SDA
Data Stable Data Change Data Stable
Figure 1. Valid Data Changes on the SDA Bus
2
FN8207.1
August 25, 2005