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| X9521 Datasheet, PDF (16/25 Pages) Xicor Inc. – Dual DCP, EEPROM Memory | |||
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X9521
TIMING DIAGRAMS
Figure 22. Bus Timing
tF
tHIGH tLOW
tR
SCL
tSU:ST
SDA IN
SDA OUT
tSU:DAT
tHD:STA
tHD:DAT
tA tDH
Figure 23. WP Pin Timing
START
SCL
Clk 1
SDA IN
WP
tSU:WP
Clk 9
tHD:WP
tSU:STO
tBUF
Figure 24. Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK
tWC
Stop
Condition
Start
Condition
16
FN8207.1
August 25, 2005
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