X9521 Datasheet, PDF (7/25 Pages) Xicor Inc. – Dual DCP, EEPROM Memory

X9521
I7 I6 I5 I4 I3 I2 I1 I0
WT 0 0 0 0 0 P1 P0
WRITE TYPE
DCP SELECT
WT^†
Description
0
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
1
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
†_{This bit has no effect when a Read operation is being performed.}
Figure 8. Instruction Byte Format
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when Vcc to the device is powered down then back
up, the “wiper position” reverts to that last written to the
DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg-
ister must first be set (See “BL1, BL0: Block Lock protec-
tion bits - (Nonvolatile)” on page 12.)
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9521 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9521.
Following the Instruction Byte, a Data Byte is issued to
the X9521 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 25).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
P1 - P0
00
01
10
11
DCPx
x=1
x=2
# Taps
Max. Data Byte
Reserved
100
Refer to Appendix 1
256
FFh
Reserved
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (15₁₀) corresponds to set-
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28₁₀) corresponds to setting the
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .
It should be noted that all writes to any DCP of the X9521
are random in nature. Therefore, the Data Byte of con-
secutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits (P1 = 0,
S ^{1 0 1 0 1 1 1 0} A WT 0 0 0 0 0 P1 P0 A ^{D7 D6 D5 D4 D3 D2 D1 D0} A S
T
C
C
CT
A
K
K
KO
R
T
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
P
Figure 9. DCP Write Command Sequence
7
FN8207.1
August 25, 2005